RTEMS CPU kit cache manager API and directives are implemented
by BSP library in shared cache_manager.c file.
If CPU_DATA_CACHE_ALIGNMENT is not defined by architecture/BSP
provided cache_.h file then most of these directives are mapped
to the dummy function. The concerned directives are for example
rtems_cache_flush_multiple_data_lines(buf, size)
rtems_cache_invalidate_multiple_data_lines(buf, size)
The Cortex-Mx and Zynq and Altera use machine family specific cache
operations (armv7m, arm-l2c-310) but most of other ARM BSPs
use shared ARM cache_.h support. But that enabled cache support
only for __ARM_ARCH_5TEJ__ in past.
This change tries to correct situation. Cache operations are
compiled for __ARM_ARCH_7A__ and __ARM_ARCH_6KZ__ core families
unconditionally now. The option to request cache operations
on BSP level has been added too - CPU_HAS_ARM_CP15_CACHE_OPERATIONS.
This way to enable cache operations is used for CSP336, CSB337, Gumstix
and SMDK2410 now. These are old ARMv4 based chips which are known
to use ARM920 or similar core and use MMU in BSP code.
The patch should have minimal impact to applications which did not
use cache manager till now. But change is massive, it is possible
that some operations defined in shared CP15 support are not compatible
and or tuned for some ARM cores groups etc.
Probability of some BSP breakages is high.
But without cache operations most of operations targeting
peripherals using DMA are broken as well as runt time dynamic
loader cannot be corrected to work on architectures using cache.
I think that highly desired enhancement correction worth the troubles
and temporal BSP breakages.
Signed-off-by: Pavel Pisa <p...@cmp.felk.cvut.cz>
---
c/src/lib/libbsp/arm/csb336/Makefile.am | 4 ++--
c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg | 2 +-
c/src/lib/libbsp/arm/csb337/Makefile.am | 4 ++--
c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg | 2 +-
c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920.cfg | 2 +-
c/src/lib/libbsp/arm/gumstix/Makefile.am | 4 ++--
c/src/lib/libbsp/arm/gumstix/make/custom/gumstix.cfg | 2 +-
c/src/lib/libbsp/arm/smdk2410/Makefile.am | 4 ++--
c/src/lib/libbsp/arm/smdk2410/make/custom/smdk2410.cfg | 2 +-
c/src/lib/libcpu/arm/shared/include/cache_.h | 4 +++-
cpukit/score/cpu/arm/rtems/score/arm.h | 4 ++++
cpukit/score/cpu/arm/rtems/score/cpu.h | 7 +++++--
12 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/c/src/lib/libbsp/arm/csb336/Makefile.am
b/c/src/lib/libbsp/arm/csb336/Makefile.am
index e2687b8..bd84a4e 100644
--- a/c/src/lib/libbsp/arm/csb336/Makefile.am
+++ b/c/src/lib/libbsp/arm/csb336/Makefile.am
@@ -51,8 +51,8 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
+libbsp_a_CPPFLAGS = -I$(srcdir)/../../../libcpu/arm/shared/include
if HAS_NETWORKING
network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
diff --git a/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg
b/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg
index 535b666..cfee78d 100644
--- a/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg
+++ b/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg
@@ -9,7 +9,7 @@ RTEMS_CPU_MODEL=mc9328mxl
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
-CPU_CFLAGS = -mcpu=arm920
+CPU_CFLAGS = -mcpu=arm920 -DCPU_HAS_ARM_CP15_CACHE_OPERATIONS
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
diff --git a/c/src/lib/libbsp/arm/csb337/Makefile.am
b/c/src/lib/libbsp/arm/csb337/Makefile.am
index 598a67f..a0797d1 100644
--- a/c/src/lib/libbsp/arm/csb337/Makefile.am
+++ b/c/src/lib/libbsp/arm/csb337/Makefile.am
@@ -88,8 +88,8 @@ endif
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
+libbsp_a_CPPFLAGS = -I$(srcdir)/../../../libcpu/arm/shared/include
if HAS_NETWORKING
network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
diff --git a/c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg
b/c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg
index a579c19..76e473e 100644
--- a/c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg
+++ b/c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg
@@ -9,7 +9,7 @@ RTEMS_CPU_MODEL=at91rm9200
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
-CPU_CFLAGS = -mcpu=arm920
+CPU_CFLAGS = -mcpu=arm920 -DCPU_HAS_ARM_CP15_CACHE_OPERATIONS
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920.cfg
b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920.cfg
index 72478f8..787cb34 100644
--- a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920.cfg
+++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920.cfg
@@ -9,7 +9,7 @@ RTEMS_CPU_MODEL=arm920
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
-CPU_CFLAGS = -mcpu=arm920
+CPU_CFLAGS = -mcpu=arm920 -DCPU_HAS_ARM_CP15_CACHE_OPERATIONS
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
diff --git a/c/src/lib/libbsp/arm/gumstix/Makefile.am
b/c/src/lib/libbsp/arm/gumstix/Makefile.am
index 708a75b..df41cd5 100644
--- a/c/src/lib/libbsp/arm/gumstix/Makefile.am
+++ b/c/src/lib/libbsp/arm/gumstix/Makefile.am
@@ -54,8 +54,8 @@ libbsp_a_SOURCES += ../shared/abort/abort.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
+libbsp_a_CPPFLAGS = -I$(srcdir)/../../../libcpu/arm/shared/include
#framebuffer
if ON_SKYEYE
diff --git a/c/src/lib/libbsp/arm/gumstix/make/custom/gumstix.cfg
b/c/src/lib/libbsp/arm/gumstix/make/custom/gumstix.cfg
index a8d9fd3..9eb6028 100644
--- a/c/src/lib/libbsp/arm/gumstix/make/custom/gumstix.cfg
+++ b/c/src/lib/libbsp/arm/gumstix/make/custom/gumstix.cfg
@@ -9,7 +9,7 @@ RTEMS_CPU_MODEL=pxa255
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
-CPU_CFLAGS = -mcpu=xscale
+CPU_CFLAGS = -mcpu=xscale -DCPU_HAS_ARM_CP15_CACHE_OPERATIONS
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
diff --git a/c/src/lib/libbsp/arm/smdk2410/Makefile.am
b/c/src/lib/libbsp/arm/smdk2410/Makefile.am
index f2bf22d..f379495 100644
--- a/c/src/lib/libbsp/arm/smdk2410/Makefile.am
+++ b/c/src/lib/libbsp/arm/smdk2410/Makefile.am
@@ -64,8 +64,8 @@ libbsp_a_SOURCES += smc/smc.h
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
+libbsp_a_CPPFLAGS = -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel \
../../../libcpu/@RTEMS_CPU@/s3c24xx/clock.rel \
diff --git a/c/src/lib/libbsp/arm/smdk2410/make/custom/smdk2410.cfg
b/c/src/lib/libbsp/arm/smdk2410/make/custom/smdk2410.cfg
index c2b9273..51654ce 100644
--- a/c/src/lib/libbsp/arm/smdk2410/make/custom/smdk2410.cfg
+++ b/c/src/lib/libbsp/arm/smdk2410/make/custom/smdk2410.cfg
@@ -9,7 +9,7 @@ RTEMS_CPU_MODEL=s3c2410
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
-CPU_CFLAGS = -mcpu=arm920t -DCPU_S3C2410
+CPU_CFLAGS = -mcpu=arm920t -DCPU_S3C2410 -DCPU_HAS_ARM_CP15_CACHE_OPERATIONS
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
diff --git a/c/src/lib/libcpu/arm/shared/include/cache_.h
b/c/src/lib/libcpu/arm/shared/include/cache_.h
index a31fc11..1c56db1 100644
--- a/c/src/lib/libcpu/arm/shared/include/cache_.h
+++ b/c/src/lib/libcpu/arm/shared/include/cache_.h
@@ -23,7 +23,9 @@
#ifndef LIBCPU_ARM_CACHE__H
#define LIBCPU_ARM_CACHE__H
-#ifdef __ARM_ARCH_5TEJ__
+#if defined(__ARM_ARCH_5TEJ__) || defined(__ARM_ARCH_7A__) || \
+ defined(__ARM_ARCH_6KZ__) || defined(CPU_HAS_ARM_CP15_CACHE_OPERATIONS)
+
#include <libcpu/arm-cp15.h>
#define CPU_DATA_CACHE_ALIGNMENT 32
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h
b/cpukit/score/cpu/arm/rtems/score/arm.h
index 334e73a..9ae7830 100644
--- a/cpukit/score/cpu/arm/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/rtems/score/arm.h
@@ -54,6 +54,10 @@ extern "C" {
#define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
#endif
+#if defined(__ARM_ARCH_7A__)
+ #define ARM_MULTILIB_CACHE_LINE_MAX_64B
+#endif
+
#if !defined(__SOFTFP__)
#if defined(__ARM_NEON__)
#define ARM_MULTILIB_VFP_D32
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 815cd95..c0c782d 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -144,8 +144,11 @@
#define CPU_STACK_GROWS_UP FALSE
-/* FIXME: Is this the right value? */
-#define CPU_CACHE_LINE_BYTES 32
+#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64B)
+ #define CPU_CACHE_LINE_BYTES 32
+#else
+ #define CPU_CACHE_LINE_BYTES 64
+#endif
#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
--
2.1.4
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