Thanks for the RFC. While I'm also interested in the questions @zhiics raised, 
I have a few more questions:

1. It seems like the major annotation process would be done by composite 
functions. Will your flow use patterns to form composite functions only? Or you 
will still have a list of supported single operators.

2. You mentioned that the codegen will generate a command stream. Would you 
ellaborate a bit more about the command stream? Is it a sequence of assembly 
code like other processors, or it's morel ike a bit-stream to program FPGAs?

Thanks.





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