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commit 532100acb5c35a006d7a395836d944f6e88b213f Author: Jerzy Kasenberg <[email protected]> AuthorDate: Tue Apr 28 15:00:22 2026 +0200 stm32h5: Add clock support function This adds functionality that aim to help enabling peripheral clocks. Signed-off-by: Jerzy Kasenberg <[email protected]> --- hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h | 370 +++++++++++++++++++++++++ hw/mcu/stm/stm32h5xx/include/mcu/stm32_clock.h | 67 +++++ hw/mcu/stm/stm32h5xx/src/stm32_clock.c | 96 +++++++ 3 files changed, 533 insertions(+) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h b/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h new file mode 100644 index 000000000..906e0ee5d --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h @@ -0,0 +1,370 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef PER_CLOCKS_H +#define PER_CLOCKS_H + +#ifndef STM32_PER_CLOCK_DEF +#error "File should not be explicitly included" +#else + +STM32_PER_CLOCK_DEF(GPDMA1); +STM32_PER_CLOCK_DEF(GPDMA2); +#ifdef SAI1 +STM32_PER_CLOCK_DEF(SAI1); +#endif +#ifdef SAI2 +STM32_PER_CLOCK_DEF(SAI2); +#endif +#ifdef SAI3 +STM32_PER_CLOCK_DEF(SAI3); +#endif +STM32_PER_CLOCK_DEF(GPIOA); +STM32_PER_CLOCK_DEF(GPIOB); +STM32_PER_CLOCK_DEF(GPIOC); +STM32_PER_CLOCK_DEF(GPIOD); +STM32_PER_CLOCK_DEF(GPIOE); +STM32_PER_CLOCK_DEF(GPIOF); +STM32_PER_CLOCK_DEF(GPIOG); +STM32_PER_CLOCK_DEF(GPIOH); +#ifdef GPIOI +STM32_PER_CLOCK_DEF(GPIOI); +#endif +STM32_PER_CLOCK_DEF(USART1); +STM32_PER_CLOCK_DEF(USART2); +STM32_PER_CLOCK_DEF(USART3); +STM32_PER_CLOCK_DEF(UART4); +STM32_PER_CLOCK_DEF(UART5); +STM32_PER_CLOCK_DEF(USART6); +#ifdef UART7 +STM32_PER_CLOCK_DEF(UART7); +#endif +#ifdef UART8 +STM32_PER_CLOCK_DEF(UART8); +#endif +#ifdef UART9 +STM32_PER_CLOCK_DEF(UART9); +#endif +#ifdef USART10 +STM32_PER_CLOCK_DEF(USART10); +#endif +#ifdef USART11 +STM32_PER_CLOCK_DEF(USART11); +#endif +STM32_PER_CLOCK_DEF(SPI1); +STM32_PER_CLOCK_DEF(SPI2); +STM32_PER_CLOCK_DEF(SPI3); +STM32_PER_CLOCK_DEF(SPI4); +#ifdef SPI5 +STM32_PER_CLOCK_DEF(SPI5); +#endif +#ifdef SPI6 +STM32_PER_CLOCK_DEF(SPI6); +#endif +STM32_PER_CLOCK_DEF(I2C1); +STM32_PER_CLOCK_DEF(I2C2); +STM32_PER_CLOCK_DEF(I2C3); +#ifdef I2C4 +STM32_PER_CLOCK_DEF(I2C4); +#endif + +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, PCLK2); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, HSI); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, CSI); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, LSE); + +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, PCLK1); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, HSI); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, CSI); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, LSE); + +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, PCLK1); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, HSI); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, CSI); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, LSE); + +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, PCLK1); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, HSI); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, CSI); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, LSE); + +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, PCLK1); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, HSI); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, CSI); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, LSE); + +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, PCLK1); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, HSI); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, CSI); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, LSE); + +#ifdef UART7 +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, PCLK1); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, HSI); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, CSI); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, LSE); +#endif + +#ifdef UART8 +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, PCLK1); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, HSI); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, CSI); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, LSE); +#endif + +#ifdef UART9 +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, PCLK1); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, HSI); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, CSI); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, LSE); +#endif + +#ifdef USART10 +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, PCLK1); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, HSI); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, CSI); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, LSE); +#endif + +#ifdef USART11 +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, PCLK1); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, HSI); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, CSI); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, LSE); +#endif + +#ifdef USART12 +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, PCLK1); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, HSI); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, CSI); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, LSE); +#endif + +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, CLKP); + +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, PCLK1); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, CLKP); + +#ifdef LPTIM3 +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, CLKP); +#endif + +#ifdef LPTIM4 +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, CLKP); +#endif + +#ifdef LPTIM5 +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, CLKP); +#endif + +#ifdef LPTIM6 +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, CLKP); +#endif + + +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PLL1Q); +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PLL2P); +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PLL3P); +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PIN); +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, CLKP); + +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PLL1Q); +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PLL2P); +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PLL3P); +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PIN); +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, CLKP); + +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PLL1Q); +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PLL2P); +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PLL3P); +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PIN); +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, CLKP); + +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, PCLK2); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, PLL2Q); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, PLL3Q); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, HSI); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, CSI); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, HSE); + +#ifdef SPI5 +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, PCLK3); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, PLL2Q); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, PLL3Q); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, HSI); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, CSI); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, HSE); +#endif + +#ifdef SPI6 +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, PCLK2); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, PLL2Q); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, PLL3Q); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, HSI); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, CSI); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, HSE); +#endif + +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, PCLK3); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, PLL2Q); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, PLL3Q); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, HSI); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, CSI); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, LSE); + +STM32_CLKSEL_DEF1(SYSTICK, CCIPR4, SYSTICKSEL, HCLKDIV8); +STM32_CLKSEL_DEF1(SYSTICK, CCIPR4, SYSTICKSEL, LSI); +STM32_CLKSEL_DEF1(SYSTICK, CCIPR4, SYSTICKSEL, LSE); + +STM32_CLKSEL_DEF1(USB, CCIPR4, USBSEL, PLL1Q); +STM32_CLKSEL_DEF1(USB, CCIPR4, USBSEL, PLL3Q); +STM32_CLKSEL_DEF1(USB, CCIPR4, USBSEL, HSI48); + +STM32_CLKSEL_DEF2(SDMMC1, CCIPR4, SDMMC1SEL, PLL1Q); +STM32_CLKSEL_DEF2(SDMMC1, CCIPR4, SDMMC1SEL, PLL2R); + +#ifdef SDMMC2 +STM32_CLKSEL_DEF2(SDMMC2, CCIPR4, SDMMC2SEL, PLL1Q); +STM32_CLKSEL_DEF2(SDMMC2, CCIPR4, SDMMC2SEL, PLL2R); +#endif + +STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, PCLK1); +STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, PLL3R); +STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, HSI); +STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, CSI); + +STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, PCLK1); +STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, PLL3R); +STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, HSI); +STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, CSI); + +STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, PCLK3); +STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, PLL3R); +STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, HSI); +STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, CSI); + +#ifdef I2C4 +STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, PCLK3); +STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, PLL3R); +STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, HSI); +STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, CSI); +#endif + +STM32_CLKSEL_DEF2(I3C1, CCIPR4, I3C1SEL, PCLK1); +STM32_CLKSEL_DEF2(I3C1, CCIPR4, I3C1SEL, PLL3R); +STM32_CLKSEL_DEF2(I3C1, CCIPR4, I3C1SEL, HSI); + +#ifdef I3C2 +STM32_CLKSEL_DEF2(I3C2, CCIPR4, I3C2SEL, PCLK3); +STM32_CLKSEL_DEF2(I3C2, CCIPR4, I3C2SEL, PLL3R); +STM32_CLKSEL_DEF2(I3C2, CCIPR4, I3C2SEL, HSI); +#endif + +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, HCLK); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, SYSCLK); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, PLL2R); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, HSE); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, HSI); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, CSI); + +STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, HSI48); +STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, PLL1Q); +STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, LSE); +STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, LSI); + +STM32_CLKSEL_DEF1(CEC, CCIPR5, CECSEL, LSE); +STM32_CLKSEL_DEF1(CEC, CCIPR5, CECSEL, LSI); +STM32_CLKSEL_DEF1(CEC, CCIPR5, CECSEL, CSI_DIV122); + +STM32_CLKSEL_DEF1(FDCAN, CCIPR5, FDCANSEL, HSE); +STM32_CLKSEL_DEF1(FDCAN, CCIPR5, FDCANSEL, PLL1Q); +STM32_CLKSEL_DEF1(FDCAN, CCIPR5, FDCANSEL, PLL2Q); + +#ifdef SAI1 +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, PLL1Q); +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, PLL2P); +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, PLL3P); +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, PIN); +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, CLKP); +#endif + +#ifdef SAI2 +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, PLL1Q); +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, PLL2P); +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, PLL3P); +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, PIN); +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, CLKP); +#endif + +#endif + +#endif diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32_clock.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_clock.h new file mode 100644 index 000000000..83b1ba0a1 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_clock.h @@ -0,0 +1,67 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef _STM32_CLOCK_H +#define _STM32_CLOCK_H + +#include <mcu/stm32_hal.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef const struct stm32_clock *stm32_clock_t; +typedef const struct stm32_clock_ops *stm32_clock_ops_t; +typedef const struct stm32_clock_src *stm32_clock_src_t; + +struct stm32_clock_ops { + void (*enable)(stm32_clock_t clock); + void (*disable)(stm32_clock_t clock); +}; + +struct stm32_clock { + stm32_clock_ops_t ops; +}; + +void stm32_clock_enable(stm32_clock_t clock); +void stm32_clock_disable(stm32_clock_t clock); + +#ifndef STM32_PER_CLOCK_DEF +#define STM32_PER_CLOCK_DEF(per) \ +extern const struct stm32_clock _##per##_clock;\ +static const struct stm32_clock *const per##_clock = &_##per##_clock; + +#define PER_CLOCK(per) per##_clock + +#define STM32_CLKSEL_DEF1(per, rcc_reg, reg_field, reg_val)\ +extern const struct stm32_clock_src _##per##_##reg_val;\ +static stm32_clock_t const per##_##reg_val __unused = (stm32_clock_t)&_##per##_##reg_val; + +#define STM32_CLKSEL_DEF2(per, rcc_reg, reg_field, reg_val)\ +extern const struct stm32_clock_src _##per##_##reg_val;\ +static stm32_clock_t const per##_##reg_val __unused = (stm32_clock_t)&_##per##_##reg_val; + +#include <mcu/per_clocks.h> +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_CLOCK_H */ diff --git a/hw/mcu/stm/stm32h5xx/src/stm32_clock.c b/hw/mcu/stm/stm32h5xx/src/stm32_clock.c new file mode 100644 index 000000000..189727389 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/stm32_clock.c @@ -0,0 +1,96 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <os/mynewt.h> +#include <mcu/stm32_hal.h> +#include <stm32h5xx_ll_rcc.h> + +#define STM32_PER_CLOCK_DEF(per) \ +void per##_clock_enable(stm32_clock_t clock) \ +{\ + __HAL_RCC_##per##_CLK_ENABLE(); \ +}\ +void per##_clock_disable(stm32_clock_t clock) \ +{\ + __HAL_RCC_##per##_CLK_ENABLE(); \ +}\ +const struct stm32_clock_ops per##_clock_ops = { \ + .enable = per##_clock_enable, \ + .disable = per##_clock_disable, \ +};\ +const struct stm32_clock _##per##_clock = { \ + .ops = &per##_clock_ops, \ +}; + +#define STM32_CLKSEL_DEF1(per, rcc_reg, reg_field, reg_val) \ +const struct stm32_clock_src _##per##_##reg_val = {\ + .base.ops = &stm32_clksel_ops,\ + .reg = &RCC->rcc_reg,\ + .mask = RCC_##rcc_reg##_##reg_field,\ + .value = LL_RCC##_##per##_CLKSOURCE_##reg_val,\ +} + +#define STM32_CLKSEL_DEF2(per, rcc_reg, reg_field, reg_val) \ +const struct stm32_clock_src _##per##_##reg_val = {\ + .base.ops = &stm32_clksel_ops,\ + .reg = &RCC->rcc_reg,\ + .mask = RCC_##rcc_reg##_##reg_field,\ + .value = (((LL_RCC_##per##_CLKSOURCE_##reg_val) >> LL_RCC_CONFIG_SHIFT) && 0xFF)\ + << RCC_##rcc_reg##_##reg_field##_Pos,\ +} + +#include <mcu/stm32_clock.h> + +void +stm32_clock_enable(stm32_clock_t clock) +{ + clock->ops->enable(clock); +} + +void +stm32_clock_disable(stm32_clock_t clock) +{ + clock->ops->disable(clock); +} + + +struct stm32_clock_src { + struct stm32_clock base; + __IO uint32_t *reg; + uint32_t mask; + uint32_t value; +}; + +void stm32_clksel_enable(stm32_clock_t clock) +{ + stm32_clock_src_t clksel = (stm32_clock_src_t)clock; + + *clksel->reg = (*clksel->reg & ~clksel->mask) | clksel->value; +} + +void stm32_clksel_disable(stm32_clock_t clock) +{ +} + +static const struct stm32_clock_ops stm32_clksel_ops = { + .enable = stm32_clksel_enable, + .disable = stm32_clksel_disable, +}; + +#include <mcu/per_clocks.h>
