llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Brandon Wu (4vtomat) <details> <summary>Changes</summary> [RISCV][VCIX] Add vcix_state to GNU inline assembly register set Resolved https://github.com/llvm/llvm-project/issues/106700. This enables inline asm to have vcix_state to be a clobbered register thus disable reordering between VCIX intrinsics and inline asm. --- Full diff: https://github.com/llvm/llvm-project/pull/106914.diff 3 Files Affected: - (modified) clang/lib/Basic/Targets/RISCV.cpp (+1-1) - (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.td (+5-1) - (added) llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll (+22) ``````````diff diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index b89109e7725d44..da6ecfb4e4022b 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -44,7 +44,7 @@ ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const { "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // CSRs - "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "vcix_state" }; // clang-format on return llvm::ArrayRef(GCCRegNames); diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 4d5c0a7bef9416..03f05c0baea3b0 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -664,5 +664,9 @@ def FRM : RISCVReg<0, "frm">; // Shadow Stack register def SSP : RISCVReg<0, "ssp">; -// Dummy VCIX state register +// Dummy VCIX state register and its register class def VCIX_STATE : RISCVReg<0, "vcix_state">; +def : RISCVRegisterClass<[XLenVT], 32, (add VCIX_STATE)> { + let RegInfos = XLenRI; + let isAllocatable = 0; +} diff --git a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll new file mode 100644 index 00000000000000..0013461d873281 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +; VCIX instructions can not reorder between each other. +define void @test_reorder(<vscale x 1 x i64> %vreg) { +; CHECK-LABEL: test_reorder: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, ma +; CHECK-NEXT: sf.vc.iv 0, 0, v8, 0 +; CHECK-NEXT: #APP +; CHECK-NEXT: sf.vc.vv 3, 0, v8, v8 +; CHECK-EMPTY: +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: ret +entry: + call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen 0, <vscale x 1 x i64> %vreg, iXLen 0, iXLen 0) + call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;", "=r,^vr,~{memory},~{vl},~{vcix_state}"(<vscale x 1 x i64> %vreg) + ret void +} `````````` </details> https://github.com/llvm/llvm-project/pull/106914 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
