================ @@ -664,5 +664,9 @@ def FRM : RISCVReg<0, "frm">; // Shadow Stack register def SSP : RISCVReg<0, "ssp">; -// Dummy VCIX state register +// Dummy VCIX state register and its register class def VCIX_STATE : RISCVReg<0, "vcix_state">; +def : RISCVRegisterClass<[XLenVT], 32, (add VCIX_STATE)> { ---------------- wangpc-pp wrote:
Why do we need a RegisterClass for it? https://github.com/llvm/llvm-project/pull/106914 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits