Sebastian Huber commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/230#note_112711 The Cortex-A53 needs special compiler flags to work around processor errata. Maybe the UltraScale+ gets an update with a new core in the future. We can name the RPU BSPs also * zynqmp_r5_lock_step * zynqmp_r5_split_0 * zynqmp_r5_split_1 The split mode and lock-step mode have different memory layouts. So, you need the different BSP variants. Also the split mode BSP has some extra tweaks in the interrupt controller support. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/230#note_112711 You're receiving this email because of your account on gitlab.rtems.org.
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