On 01/19/2017 09:11 PM, Lux, Jim (337C) wrote:
On 1/19/17, 4:29 PM, "Beowulf on behalf of Lukasz Salwinski"
<beowulf-boun...@beowulf.org on behalf of luk...@mbi.ucla.edu> wrote:
On 01/19/2017 02:09 PM, Lux, Jim (337C) wrote:
-----Original Message-----
From: Beowulf [mailto:beowulf-boun...@beowulf.org] On Behalf Of Andrew
M.A. Cater
Sent: Thursday, January 19, 2017 12:49 PM
To: beowulf@beowulf.org
Subject: Re: [Beowulf] Mobos for portable use
[...]
(I just found that at least a while ago, Xilinx supported clusters for
some of their design tools.. Since right now the design I'm working
with takes an hour to synthesize (on a single machine), I'm going to
look further - it has been a real rate limiter in the lab, because it
makes the test, new design, load, test cycle a lot longer.)
it looks like current (vivado 16.4) synthesis program hasn't been
parallelized - it's strictly single threaded and so uses just one
core... :o/ I've recently benchmarked a few i5 & i7 workstations
- there seem to be very little differences (maybe 10-20%) between
CPUs released over last ~4-5 years :o/
lukasz
yeah, on further investigation, the parallelized part is the iterative
³try lots of options² which isn¹t much use.
I¹ve got the design, I don¹t need to optimize a parameter.
to my knowledge, parts of place/route use more than one core. I'm
guessing it might be because these were, from the very beginning, series
of independent MonteCarlo-like runs that were easy to parallelize.
lukasz
--
-------------------------------------------------------------------------
Lukasz Salwinski PHONE: 310-825-1402
UCLA-DOE Institute FAX: 310-206-3914
UCLA, Los Angeles EMAIL: luk...@mbi.ucla.edu
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