On 02.08.2024 09:41, Chen, Jiqian wrote:
> On 2024/8/2 14:25, Jan Beulich wrote:
>> On 02.08.2024 04:55, Chen, Jiqian wrote:
>>> On 2024/7/31 23:55, Roger Pau Monné wrote:
>>>> On Mon, Jul 08, 2024 at 07:41:18PM +0800, Jiqian Chen wrote:
>>>>> @@ -305,6 +312,15 @@ struct physdev_pci_device {
>>>>> typedef struct physdev_pci_device physdev_pci_device_t;
>>>>> DEFINE_XEN_GUEST_HANDLE(physdev_pci_device_t);
>>>>>
>>>>> +struct pci_device_state_reset {
>>>>> + physdev_pci_device_t dev;
>>>>> +#define PCI_DEVICE_STATE_RESET_COLD 0
>>>>> +#define PCI_DEVICE_STATE_RESET_WARM 1
>>>>> +#define PCI_DEVICE_STATE_RESET_HOT 2
>>>>> +#define PCI_DEVICE_STATE_RESET_FLR 3
>>>>> + uint32_t reset_type;
>>>>
>>>> This might want to be a flags field, with the low 2 bits (or maybe 3
>>>> bits to cope if more rest modes are added in the future) being used to
>>>> signal the reset type. We can always do that later if flags need to
>>>> be added.
>>> Do you mean this?
>>> +struct pci_device_state_reset {
>>> + physdev_pci_device_t dev;
>>> +#define _PCI_DEVICE_STATE_RESET_COLD 0
>>> +#define PCI_DEVICE_STATE_RESET_COLD (1U<<_PCI_DEVICE_STATE_RESET_COLD)
>>> +#define _PCI_DEVICE_STATE_RESET_WARM 1
>>> +#define PCI_DEVICE_STATE_RESET_WARM (1U<<_PCI_DEVICE_STATE_RESET_WARM)
>>> +#define _PCI_DEVICE_STATE_RESET_HOT 2
>>> +#define PCI_DEVICE_STATE_RESET_HOT (1U<<_PCI_DEVICE_STATE_RESET_HOT)
>>> +#define _PCI_DEVICE_STATE_RESET_FLR 3
>>> +#define PCI_DEVICE_STATE_RESET_FLR (1U<<_PCI_DEVICE_STATE_RESET_FLR)
>>> + uint32_t reset_type;
>>> +};
>>
>> That's four bits, not two. I'm pretty sure Roger meant to keep the enum-
>> like #define-s, but additionally define a 2-bit mask constant (0x3). I
>> don't think it needs to be three bits right away - we can decide what to
>> do there when any of the higher bits are to be assigned a meaning.
> Like this?
> struct pci_device_state_reset {
> physdev_pci_device_t dev;
> #define PCI_DEVICE_STATE_RESET_COLD 0x0
> #define PCI_DEVICE_STATE_RESET_WARM 0x1
> #define PCI_DEVICE_STATE_RESET_HOT 0x2
> #define PCI_DEVICE_STATE_RESET_FLR 0x3
> #define PCI_DEVICE_STATE_RESET_MASK 0x3
> uint32_t flags;
> };
Yes, with the last #define adjusted such that columns align.
Jan
