Introduce a handler for the PCI status register, with ability to mask the capabilities bit. The status register is write-1-to-clear, so introduce handling for this type of register in vPCI.
Signed-off-by: Stewart Hildebrand <[email protected]> --- v2->v3: * new patch --- xen/drivers/vpci/header.c | 24 +++++++++++++++++++++++ xen/drivers/vpci/vpci.c | 41 +++++++++++++++++++++++++++++---------- xen/include/xen/vpci.h | 9 +++++++++ 3 files changed, 64 insertions(+), 10 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index b531ab03cec1..7061b85e337b 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -413,6 +413,17 @@ static void cf_check cmd_write( pci_conf_write16(pdev->sbdf, reg, cmd); } +static uint32_t cf_check status_read(const struct pci_dev *pdev, + unsigned int reg, void *data) +{ + struct vpci_header *header = data; + + if ( header->mask_cap_list ) + return pci_conf_read16(pdev->sbdf, reg) & ~(PCI_STATUS_CAP_LIST); + + return pci_conf_read16(pdev->sbdf, reg); +} + static void cf_check bar_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { @@ -556,6 +567,11 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; + rc = vpci_add_rw1c_register(pdev->vpci, status_read, vpci_hw_write16, + PCI_STATUS, 2, header); + if ( rc ) + return rc; + if ( !is_hardware_domain(pdev->domain) ) { if ( !(pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST) ) @@ -583,6 +599,14 @@ static int cf_check init_bars(struct pci_dev *pdev) next &= ~3; + if ( !next ) + /* + * If we don't have any supported capabilities to expose to the + * guest, mask the PCI_STATUS_CAP_LIST bit in the status + * register. + */ + header->mask_cap_list = true; + while ( next && ttl ) { uint8_t pos = next; diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 4a96aa50494d..a34d85f4ed3c 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -29,6 +29,7 @@ struct vpci_register { unsigned int offset; void *private; struct list_head node; + bool rw1c : 1; }; #ifdef __XEN__ @@ -157,9 +158,15 @@ uint32_t cf_check vpci_hw_read32( return pci_conf_read32(pdev->sbdf, reg); } -int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, - vpci_write_t *write_handler, unsigned int offset, - unsigned int size, void *data) +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) +{ + pci_conf_write16(pdev->sbdf, reg, val); +} + +static int _vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data, bool rw1c) { struct list_head *prev; struct vpci_register *r; @@ -179,6 +186,7 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, r->size = size; r->offset = offset; r->private = data; + r->rw1c = rw1c; spin_lock(&vpci->lock); @@ -205,6 +213,22 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, return 0; } +int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data) +{ + return _vpci_add_register(vpci, read_handler, write_handler, offset, size, + data, false); +} + +int vpci_add_rw1c_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data) +{ + return _vpci_add_register(vpci, read_handler, write_handler, offset, size, + data, true); +} + int vpci_remove_register(struct vpci *vpci, unsigned int offset, unsigned int size) { @@ -419,11 +443,6 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size) /* * Perform a maybe partial write to a register. - * - * Note that this will only work for simple registers, if Xen needs to - * trap accesses to rw1c registers (like the status PCI header register) - * the logic in vpci_write will have to be expanded in order to correctly - * deal with them. */ static void vpci_write_helper(const struct pci_dev *pdev, const struct vpci_register *r, unsigned int size, @@ -433,9 +452,11 @@ static void vpci_write_helper(const struct pci_dev *pdev, if ( size != r->size ) { - uint32_t val; + uint32_t val = 0; + + if ( !r->rw1c ) + val = r->read(pdev, r->offset, r->private); - val = r->read(pdev, r->offset, r->private); data = merge_result(val, data, size, offset); } diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 17fd252746ec..518d381b2df7 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -37,6 +37,11 @@ int __must_check vpci_add_register(struct vpci *vpci, vpci_write_t *write_handler, unsigned int offset, unsigned int size, void *data); +int __must_check vpci_add_rw1c_register(struct vpci *vpci, + vpci_read_t *read_handler, + vpci_write_t *write_handler, + unsigned int offset, unsigned int size, + void *data); int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offset, unsigned int size); @@ -55,6 +60,8 @@ uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( const struct pci_dev *pdev, unsigned int reg, void *data); +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data); /* * Check for pending vPCI operations on this vcpu. Returns true if the vcpu @@ -99,6 +106,8 @@ struct vpci { * upon to know whether BARs are mapped into the guest p2m. */ bool bars_mapped : 1; + /* Store whether to hide all capabilities from the guest. */ + bool mask_cap_list : 1; /* FIXME: currently there's no support for SR-IOV. */ } header; -- 2.41.0
