Hi, I wanted to run RTEMS on HiFive Unleashed (rv64imac/imafdc) from QSPI memory. Since I want to boot RTEMS from QSPI memory I placed PLL settings and DDR timing training from SiFive first stage bootloader into RTEMS booting procedure.
Booting procedure passes RTEMS linkersets initialization, but it fails in the first context switch. Store conditional instruction triggers the Store/AMO fault exception. Instruction "CLEAR_RESERVATIONS a2" that is actually sw.c zero, zero, (a2) triggers that fault (placed in riscv-context-switch.S line 139). Register a2 holds and address somewhere in RAM memory that should be unprotected. Store should be done on normal R/W memory placed in RAM. I do not configure any type of physical memory protection for the CPU. Is there any way to check existing memory protection configuration on RISCV (registers readout or something like that)? Is there anything else that could trigger store conditional instruction to fail that way except PMP? Best regards, Nenad _______________________________________________ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
