On 02/04/2019 16:28, Catalin Demergian wrote:
I did more tests. it seems not the same type of error happens every
time. I got the _Configuration_Scheduler_priority_dflt a few times,
but also
the 'enabled interrupts when they suppposed to be disabled' happened
as well
RTEMS_INLINE_ROUTINE void _Scheduler_priority_Ready_queue_enqueue(
Chain_Node *node,
Scheduler_priority_Ready_queue *ready_queue,
Priority_bit_map_Control *bit_map
)
{
Chain_Control *ready_chain = ready_queue->ready_chain;
//_Assert(_ISR_Get_level() != 0);
if(_ISR_Get_level() == 0)
gIntrErrs++;
cnt_before = _Chain_Node_count_unprotected(ready_chain);
_Chain_Append_unprotected( ready_chain, node );
cnt_after = _Chain_Node_count_unprotected(ready_chain);
if(cnt_after != cnt_before + 1)
gIntrErrs++;
_Priority_bit_map_Add( bit_map, &ready_queue->Priority_map );
}
.. and I modified the cpuuse command to display gIntrErrs
What do you get if you use separate counters for these errors?
I still believe that you use some interrupts with a too high priority.
What happens if you apply the attached patch?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
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Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>From 80538af274c1e96279e839d4f864c64ce16358b8 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.hu...@embedded-brains.de>
Date: Wed, 3 Apr 2019 07:25:15 +0200
Subject: [PATCH] Disable the highest priority interrupts
---
cpukit/score/cpu/arm/include/rtems/score/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index a537a4a4b6..aaf6f28b00 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -305,7 +305,7 @@ static inline uint32_t arm_interrupt_disable( void )
: [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
);
#elif defined(ARM_MULTILIB_ARCH_V7M)
- uint32_t basepri = 0x80;
+ uint32_t basepri = 0x1;
__asm__ volatile (
"mrs %[level], basepri\n"
--
2.16.4
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