Dear Sebastian, I think that my BSP code is correct. I attached this.
This code was made for referencing FreeBSD's i.MX6Q BSP code. I guess that my issue is related with additional i.MX6Q system configuration. Best Regards, JunBeom -----Original Message----- From: Sebastian Huber [mailto:sebastian.hu...@embedded-brains.de] Sent: Wednesday, September 27, 2017 3:51 PM To: JunBeom Kim (Coressent Kr.) <jb...@coressentkorea.co.kr>; users@rtems.org Subject: Re: Coressent Korea - Freescale i.MX6 RTEMS/Qt SDK Release Information. On 27/09/17 08:38, JunBeom Kim (Coressent Kr.) wrote: > I am still working for porting i.MX6Q FEC driver after I added FreeBSD's > i.MX6 FEC driver code on rtems-libbsd. > > But, Because my custom board have different PHY chip(RTL8201E), I did't port > FEC drier on i.MX6Q board. I used fdt loading method, too. > > If possible, please could you let me know i.MX6Q hardware board information > which you are successful for porting FEC driver ? I don't have an i.MX6Q. I have two i.MX7D boards: https://www.tq-group.com/en/products/product-details/prod/embedded-modul-tqma7x/extb/Main/productdetail/ https://www.nxp.com/support/developer-resources/hardware-development-tools/sabre-development-system/sabre-board-for-smart-devices-based-on-the-i.mx-7dual-applications-processors:MCIMX7SABRE > > On referencing, I am working to port SMP for i.MX6Q. > At this time, current version is not stable. I am looking technical reason. The i.MX6Q uses a Cortex A9. We already have SMP support for this core on other BSPs (Xilinx Zync, Altera Cyclone V, Realview). You only have to implement the _CPU_SMP_Start_processor() function. The code for this is available in FreeBSD for example. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
/* * Copyright (c) 2014 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 * 82178 Puchheim * Germany * <i...@embedded-brains.de> * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.org/license/LICENSE. */ #include <rtems/score/smpimpl.h> #include <bsp.h> #include <bsp/start.h> #define SRC_PHYSBASE 0x020d8000 #define SRC_CONTROL_REG 0x00 #define SRC_CONTROL_C1ENA_SHIFT 22 /* Bit for Core 1 enable */ #define SRC_CONTROL_C1RST_SHIFT 14 /* Bit for Core 1 reset */ #define SRC_GPR0_C1FUNC 0x20 /* Register for Core 1 entry func */ #define SRC_GPR1_C1ARG 0x24 /* Register for Core 1 entry arg */ bool _CPU_SMP_Start_processor(uint32_t cpu_index) { uint32_t value; bool started; if (cpu_index != 0) { mmio32_write(SRC_PHYSBASE + (SRC_GPR0_C1FUNC+8*cpu_index), _start); mmio32_write(SRC_PHYSBASE + (SRC_GPR1_C1ARG+8*cpu_index), 0); value = mmio32_read(SRC_PHYSBASE + SRC_CONTROL_REG); value |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + cpu_index )) | ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + cpu_index))); mmio32_write(SRC_PHYSBASE + SRC_CONTROL_REG, value); _ARM_Data_synchronization_barrier(); _ARM_Instruction_synchronization_barrier(); _ARM_Send_event(); } return _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0); }
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