The diff below removes support for 386SX/DX processors. We already claim
we don't support anything older than a Pentium so there's no point to keep
this code.
The main code change is in locore0.S and is to stop checking if the CPU
we're on has the alignment check (PSL_AC) flag.
The rest of the diff is about deleting ancient comments about how things
worked before the 486. 2 files under arch/amd64 are updated to keep them
in sync with arch/i386.
The 486 (which was launched in 1989) added a small number of changes over
a system with an 80386 + 80387 co-processor:
- an alignment check (AC) flag in EFLAGS; this is how we check for 386 vs
486 and this is what we're removing
- new bits in CR0; 386 CPUs did not support ring0 write protection
- new bits in CR3
- 3 new userland instructions: bswap / cmpxchg / xadd
- 3 new kernel mode instructions: invd / wbinvd / invlpg
I can't imagine the current code could possibly work on a real 386sx or
386dx CPU since we seem to unconditionally call 5 out of the 6
instructions mentioned above unconditionally. (The 6th instruction "invd"
is used in locore0.S, but it looks like that one does check that we're on
a 486 or newer CPU first).
fwiw, it appears that Linux 3.8 dropped support for 386 CPUs back in 2012.
ok?
Index: amd64/amd64/lapic.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/lapic.c,v
retrieving revision 1.59
diff -u -p -u -r1.59 lapic.c
--- amd64/amd64/lapic.c 31 Aug 2021 15:53:36 -0000 1.59
+++ amd64/amd64/lapic.c 28 Jul 2022 01:41:15 -0000
@@ -213,9 +213,7 @@ lapic_map(paddr_t lapic_base)
va = (vaddr_t)&local_apic;
} else {
/*
- * Map local apic. If we have a local apic, it's safe to
- * assume we're on a 486 or better and can use invlpg and
- * non-cacheable PTEs
+ * Map local apic.
*
* Whap the PTE "by hand" rather than calling pmap_kenter_pa
* because the latter will attempt to invoke TLB shootdown
Index: amd64/stand/mbr/mbr.S
===================================================================
RCS file: /cvs/src/sys/arch/amd64/stand/mbr/mbr.S,v
retrieving revision 1.7
diff -u -p -u -r1.7 mbr.S
--- amd64/stand/mbr/mbr.S 27 Jun 2022 16:10:09 -0000 1.7
+++ amd64/stand/mbr/mbr.S 28 Jul 2022 01:41:16 -0000
@@ -112,7 +112,7 @@ start:
*
* Accordingly, this code will fail on very early 8086/88s, but
* nick@ will just have to live with it. Others will note that
- * we require an 80386 (or compatible) or above processor, anyway.
+ * we require at least a Pentium compatible processor anyway.
*/
/* cli */
movw %ax, %ss
Index: i386/i386/cpu.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/cpu.c,v
retrieving revision 1.108
diff -u -p -u -r1.108 cpu.c
--- i386/i386/cpu.c 21 Feb 2022 10:24:28 -0000 1.108
+++ i386/i386/cpu.c 28 Jul 2022 01:41:18 -0000
@@ -406,8 +406,7 @@ cpu_init(struct cpu_info *ci)
patinit(ci);
/*
- * Enable ring 0 write protection (486 or above, but 386
- * no longer supported).
+ * Enable ring 0 write protection
*/
lcr0(rcr0() | CR0_WP);
Index: i386/i386/lapic.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/lapic.c,v
retrieving revision 1.48
diff -u -p -u -r1.48 lapic.c
--- i386/i386/lapic.c 11 Jun 2021 05:33:16 -0000 1.48
+++ i386/i386/lapic.c 28 Jul 2022 01:41:18 -0000
@@ -85,8 +85,7 @@ lapic_map(paddr_t lapic_base)
tpr = lapic_tpr;
/*
- * Map local apic. If we have a local apic, it's safe to assume
- * we're on a 486 or better and can use invlpg and non-cacheable PTEs
+ * Map local apic.
*
* Whap the PTE "by hand" rather than calling pmap_kenter_pa because
* the latter will attempt to invoke TLB shootdown code just as we
Index: i386/i386/locore.s
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/locore.s,v
retrieving revision 1.194
diff -u -p -u -r1.194 locore.s
--- i386/i386/locore.s 3 Jan 2022 00:44:30 -0000 1.194
+++ i386/i386/locore.s 28 Jul 2022 01:41:18 -0000
@@ -266,7 +266,7 @@ _C_LABEL(lapic_tpr):
.long 0
#endif
-_C_LABEL(cpu): .long 0 # are we 386, 386sx, 486, 586 or 686
+_C_LABEL(cpu): .long 0 # are we 486, 586 or 686
_C_LABEL(cpu_id): .long 0 # saved from 'cpuid' instruction
_C_LABEL(cpu_pae): .long 0 # are we using PAE paging mode?
_C_LABEL(cpu_miscinfo): .long 0 # misc info (apic/brand id)
from 'cpuid'
Index: i386/i386/locore0.S
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/locore0.S,v
retrieving revision 1.6
diff -u -p -u -r1.6 locore0.S
--- i386/i386/locore0.S 7 Jul 2022 00:56:46 -0000 1.6
+++ i386/i386/locore0.S 28 Jul 2022 01:41:18 -0000
@@ -115,27 +115,6 @@ start: movw $0x1234,0x472 # warm
boot
/* Find out our CPU type. */
-.Ltry386: /* Try to toggle alignment check flag; does not exist on 386. */
- pushfl
- popl %eax
- movl %eax,%ecx
- orl $PSL_AC,%eax
- pushl %eax
- popfl
- pushfl
- popl %eax
- xorl %ecx,%eax
- andl $PSL_AC,%eax
- pushl %ecx
- popfl
-
- testl %eax,%eax
- jnz .Ltry486
-
-.Lis386:
- movl $CPU_386,RELOC(_C_LABEL(cpu))
- jmp 2f
-
.Ltry486: /* Try to toggle identification flag; does not exist on early
486s. */
pushfl
popl %eax
Index: i386/i386/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v
retrieving revision 1.651
diff -u -p -u -r1.651 machdep.c
--- i386/i386/machdep.c 27 Jul 2022 01:44:25 -0000 1.651
+++ i386/i386/machdep.c 28 Jul 2022 01:41:19 -0000
@@ -498,10 +498,6 @@ char cpu_model[120];
* We deal with the rest in a different way.
*/
const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = {
- { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386,
- NULL}, /* CPU_386SX */
- { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386,
- NULL}, /* CPU_386 */
{ CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486,
NULL}, /* CPU_486SX */
{ CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486,
@@ -513,7 +509,6 @@ const struct cpu_nocpuid_nameclass i386_
};
const char *classnames[] = {
- "386",
"486",
"586",
"686"
@@ -1673,7 +1668,7 @@ void
identifycpu(struct cpu_info *ci)
{
const char *name, *modifier, *vendorname, *token;
- int class = CPUCLASS_386, vendor, i, max;
+ int class = CPUCLASS_486, vendor, i, max;
int family, model, step, modif, cachesize;
const struct cpu_cpuid_nameclass *cpup = NULL;
char *brandstr_from, *brandstr_to;
@@ -2078,19 +2073,13 @@ identifycpu(struct cpu_info *ci)
cpu_class = class;
- if (cpu_class == CPUCLASS_386) {
- printf("WARNING: 386 (possibly unknown?) cpu class, assuming
486\n");
- cpu_class = CPUCLASS_486;
- }
-
ci->cpu_class = class;
if (cpu == CPU_486DLC)
printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n");
/*
- * Enable ring 0 write protection (486 or above, but 386
- * no longer supported).
+ * Enable ring 0 write protection
*/
lcr0(rcr0() | CR0_WP);
Index: i386/include/cputypes.h
===================================================================
RCS file: /cvs/src/sys/arch/i386/include/cputypes.h,v
retrieving revision 1.12
diff -u -p -u -r1.12 cputypes.h
--- i386/include/cputypes.h 27 Jul 2022 01:44:25 -0000 1.12
+++ i386/include/cputypes.h 28 Jul 2022 01:41:19 -0000
@@ -32,7 +32,6 @@
* Classes of Processor
*/
-#define CPUCLASS_386 0
#define CPUCLASS_486 1
#define CPUCLASS_586 2
#define CPUCLASS_686 3
@@ -42,8 +41,6 @@
* that might not have a cpuid instruction.
*/
-#define CPU_386SX 0 /* Intel 80386SX */
-#define CPU_386 1 /* Intel 80386DX */
#define CPU_486SX 2 /* Intel 80486SX */
#define CPU_486 3 /* Intel 80486DX */
#define CPU_486DLC 4 /* Cyrix 486DLC */
Index: i386/stand/mbr/mbr.S
===================================================================
RCS file: /cvs/src/sys/arch/i386/stand/mbr/mbr.S,v
retrieving revision 1.25
diff -u -p -u -r1.25 mbr.S
--- i386/stand/mbr/mbr.S 27 Jun 2022 16:10:09 -0000 1.25
+++ i386/stand/mbr/mbr.S 28 Jul 2022 01:41:20 -0000
@@ -112,7 +112,7 @@ start:
*
* Accordingly, this code will fail on very early 8086/88s, but
* nick@ will just have to live with it. Others will note that
- * we require an 80386 (or compatible) or above processor, anyway.
+ * we require at least a Pentium compatible processor anyway.
*/
/* cli */
movw %ax, %ss
