On Sun, Jul 24, 2022 at 2:55 AM Jonathan Gray <j...@jsg.id.au> wrote: > > On Sun, Jul 24, 2022 at 02:16:23AM -0400, Daniel Dickman wrote: > > http://datasheets.chipdb.org/Rise/ > > > > Quoting the data sheet from this link: > > > > “The CMPXCHG8B instruction is supported and always enabled on the Rise > > mP6 processor; however, the default CPUID function bit is set to 0 to > > circumvent a reported bug in Windows NT” > > > > I don’t think we have a workaround for this quirk so I’m not sure > > there’s value in keeping the cpu ID code. > > The kernel shows if the CX8 bit is set, but doesn't use it otherwise.
Agree. I think on this CPU the only consequence is that CX8 won't be shown in dmesg. The quirk needed would be to detect the Rise CPU and force showing CX8. But probably no real consequence beyond that as you say. > The toolchain assumes it exists as we default to -march=i586 since 2020. > I'd expect a mP6 to boot just not be as recognised after the diff. Makes sense. > > Still ok with the original diff. Will commit soon unless someone shows up saying they have a Rise CPU and they'd like to keep this code.
