On Sat, Jul 23, 2022 at 02:13:27PM -0400, Daniel Dickman wrote: > The Rise mp6 was a short lived processor that was announced around 20+ > years and didn't make it to market. > > I think we can delete the cpu identification for this cpu at this point. > > ok?
I am ok with removing it, but I think it did ship. https://github.com/InstLatx64/InstLatx64/tree/master/RiseRiseRise http://datasheets.chipdb.org/Rise/ BIOS Writer's Guide: iDRAGON mP6 MICROPROCESSOR family 5 model 0 RiSE iDragon (0.25 um) family 5 model 2 RiSE iDragon (0.18 um) family 5 model 8 RiSE iDragon II (0.25 um) family 5 model 9 RiSE iDragon II (0.18 um) https://www.pcengines.ch/platform.htm SIS 55x CPU: Rise MP6 "Pentium class", 200 to 250 MHz, 8K I-Cache + 8K D-Cache STPC Vega CPU: Rise MP6 "Pentium II class" core, up to 250 MHz, 8K I-Cache + 8K D-Cache both SiS 55x and DM&P Vortex86 appear to use "SiS SiS SiS ". not sure what the STPC Vega would show as > > Index: i386/machdep.c > =================================================================== > RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v > retrieving revision 1.650 > diff -u -p -u -r1.650 machdep.c > --- i386/machdep.c 12 Jul 2022 05:45:49 -0000 1.650 > +++ i386/machdep.c 23 Jul 2022 18:02:05 -0000 > @@ -782,41 +782,6 @@ const struct cpu_cpuid_nameclass i386_cp > } } > }, > { > - "RiseRiseRise", > - CPUVENDOR_RISE, > - "Rise", > - /* Family 4, not available from Rise */ > - { { > - CPUCLASS_486, > - { > - 0, 0, 0, 0, 0, 0, 0, 0, > - 0, 0, 0, 0, 0, 0, 0, 0, > - "486 class" /* Default */ > - }, > - NULL > - }, > - /* Family 5 */ > - { > - CPUCLASS_586, > - { > - "mP6", 0, "mP6", 0, 0, 0, 0, 0, > - 0, 0, 0, 0, 0, 0, 0, 0, > - "mP6" /* Default */ > - }, > - NULL > - }, > - /* Family 6, not yet available from Rise */ > - { > - CPUCLASS_686, > - { > - 0, 0, 0, 0, 0, 0, 0, 0, > - 0, 0, 0, 0, 0, 0, 0, 0, > - "686 class" /* Default */ > - }, > - NULL > - } } > - }, > - { > "GenuineTMx86", > CPUVENDOR_TRANSMETA, > "Transmeta", > Index: include/cputypes.h > =================================================================== > RCS file: /cvs/src/sys/arch/i386/include/cputypes.h,v > retrieving revision 1.11 > diff -u -p -u -r1.11 cputypes.h > --- include/cputypes.h 7 Jul 2022 00:56:46 -0000 1.11 > +++ include/cputypes.h 23 Jul 2022 18:02:05 -0000 > @@ -63,7 +63,6 @@ > #define CPUVENDOR_CYRIX 1 > #define CPUVENDOR_AMD 3 > #define CPUVENDOR_IDT 4 > -#define CPUVENDOR_RISE 5 > #define CPUVENDOR_TRANSMETA 6 > #define CPUVENDOR_NS 7 > #define CPUVENDOR_VIA 8 > >
