On Thu, Nov 25, 2010 at 07:13:04PM +0100, Henning Brauer wrote:
> * Claudio Jeker <cje...@diehard.n-r-g.com> [2010-11-25 17:04]:
> > I doubt that there is a measurable performance difference on
> > i386/amd64.
>
> yeah, well, "doubt". pls run a quick test.
>
Well this was not "quick" but I finally finsihed the testing.
Tested with packet generator set to a packet size of 512B.
All test were done on the same machine using the dual port ix(4) as
interface. Forwarding performance measured with pf disabled, no
POOL_DEBUG and a pool fix for the mcl2k pool for i386.
No other fiddling was done. dmesg of the box is below.
The numbers are the top forwarding speeds as measured by the packet
generator right before livelock detection would kick in (which increases
packet loss and lowers the throughput).
amd64:
GENERIC: TX 428767 RX 428780 pps 18.25% line rate
GENERIC.MP: TX 417020 RX 417044 pps 17.75% line rate
with netisr diff:
GENERIC: TX 427622 RX 427173 pps 18.20% line rate
GENERIC.MP: TX 417020 RX 416997 pps 17.75% line rate
i386:
GENERIC: TX 440514 RX 440403 pps 18.75% line rate
GENERIC.MP: TX 428768 RX 428790 pps 18.25% line rate
with netisr diff:
GENERIC: TX 425330 RX 425320 pps 18.10% line rate
GENERIC.MP: TX 415875 RX 415619 pps 17.70% line rate
Btw. as this shows amd64 and i386 are more or less equal in performance.
i386 is a tiny little bit faster.
Diff used attached as well. I will commit this version in the next days
later on an atomic_load_and_clear_int() function will be used to help
hppa.
--
:wq Claudio
OpenBSD 4.8-current (GENERIC.MP) #2: Mon Dec 20 14:54:04 CET 2010
r...@foo.vantronix.net:/usr/src/sys/arch/i386/compile/GENERIC.MP
cpu0: Intel(R) Xeon(R) CPU E5504 @ 2.00GHz ("GenuineIntel" 686-class) 2.01 GHz
cpu0:
FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,DCA,SSE4.1,SSE4.2,POPCNT
real mem = 3211730944 (3062MB)
avail mem = 3149099008 (3003MB)
mainbus0 at root
bios0 at mainbus0: AT/286+ BIOS, date 12/31/99, BIOS32 rev. 0 @ 0xf0010, SMBIOS
rev. 2.5 @ 0x9a800 (81 entries)
bios0: vendor HP version "O33" date 12/03/2009
bios0: HP ProLiant DL160 G6
acpi0 at bios0: rev 2
acpi0: sleep states S0 S4 S5
acpi0: tables DSDT FACP APIC SPCR MCFG SPMI SLIC BOOT OEMB HPET SSDT EINJ BERT
ERST HEST
acpi0: wakeup devices NPE1(S4) NPE2(S4) NPE3(S4) NPE4(S4) NPE5(S4) NPE6(S4)
NPE7(S4) NPE8(S4) NPE9(S4) NPEA(S4) P0P1(S4) USB0(S4) USB1(S4) USB2(S4)
USB5(S4) EUSB(S4) USB3(S4) USB4(S4) USB6(S4) USBE(S4) GBE_(S4) P0P4(S4)
P0P5(S4) P0P6(S4) P0P7(S4) P0P8(S4) P0P9(S4) SLPB(S4)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 16 (boot processor)
cpu0: apic clock running at 133MHz
cpu1 at mainbus0: apid 18 (application processor)
cpu1: Intel(R) Xeon(R) CPU E5504 @ 2.00GHz ("GenuineIntel" 686-class) 2.01 GHz
cpu1:
FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,DCA,SSE4.1,SSE4.2,POPCNT
cpu2 at mainbus0: apid 20 (application processor)
cpu2: Intel(R) Xeon(R) CPU E5504 @ 2.00GHz ("GenuineIntel" 686-class) 2.01 GHz
cpu2:
FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,DCA,SSE4.1,SSE4.2,POPCNT
cpu3 at mainbus0: apid 22 (application processor)
cpu3: Intel(R) Xeon(R) CPU E5504 @ 2.00GHz ("GenuineIntel" 686-class) 2.01 GHz
cpu3:
FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,DCA,SSE4.1,SSE4.2,POPCNT
ioapic0 at mainbus0: apid 1 pa 0xfec00000, version 20, 24 pins
ioapic0: misconfigured as apic 2, remapped to apid 1
ioapic1 at mainbus0: apid 3 pa 0xfec8a000, version 20, 24 pins
ioapic1: misconfigured as apic 4, remapped to apid 3
acpihpet0 at acpi0: 14318179 Hz
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus 8 (NPE1)
acpiprt2 at acpi0: bus -1 (NPE2)
acpiprt3 at acpi0: bus 7 (NPE3)
acpiprt4 at acpi0: bus -1 (NPE4)
acpiprt5 at acpi0: bus -1 (NPE5)
acpiprt6 at acpi0: bus -1 (NPE6)
acpiprt7 at acpi0: bus 6 (NPE7)
acpiprt8 at acpi0: bus -1 (NPE8)
acpiprt9 at acpi0: bus 5 (NPE9)
acpiprt10 at acpi0: bus 4 (NPEA)
acpiprt11 at acpi0: bus 3 (P0P4)
acpiprt12 at acpi0: bus -1 (BR1B)
acpiprt13 at acpi0: bus 2 (P0P8)
acpicpu0 at acpi0: C3, C2, C1, PSS
acpicpu1 at acpi0: C3, C2, C1, PSS
acpicpu2 at acpi0: C3, C2, C1, PSS
acpicpu3 at acpi0: C3, C2, C1, PSS
acpibtn0 at acpi0: SLPB
acpibtn1 at acpi0: PWRB
bios0: ROM list: 0xc0000/0x8000 0xc8000/0x1000
ipmi at mainbus0 not configured
cpu0: Enhanced SpeedStep 2001 MHz: speeds: 2000, 1867, 1733, 1600 MHz
pci0 at mainbus0 bus 0: configuration mode 1 (bios)
pchb0 at pci0 dev 0 function 0 "Intel 5520 Host" rev 0x13
ppb0 at pci0 dev 1 function 0 "Intel X58 PCIE" rev 0x13
pci1 at ppb0 bus 8
ppb1 at pci0 dev 3 function 0 "Intel X58 PCIE" rev 0x13
pci2 at ppb1 bus 7
ix0 at pci2 dev 0 function 0 "Intel 10GbE SFP+ (82599)" rev 0x01: apic 3 int 0
(irq 10), address 00:1b:21:57:b1:7c
ix1 at pci2 dev 0 function 1 "Intel 10GbE SFP+ (82599)" rev 0x01: apic 3 int 10
(irq 5), address 00:1b:21:57:b1:7d
ppb2 at pci0 dev 7 function 0 "Intel X58 PCIE" rev 0x13
pci3 at ppb2 bus 6
ppb3 at pci0 dev 9 function 0 "Intel X58 PCIE" rev 0x13
pci4 at ppb3 bus 5
em0 at pci4 dev 0 function 0 "Intel PRO/1000 (82576)" rev 0x01: apic 3 int 8
(irq 10), address d8:d3:85:65:82:c2
em1 at pci4 dev 0 function 1 "Intel PRO/1000 (82576)" rev 0x01: apic 3 int 18
(irq 5), address d8:d3:85:65:82:c3
ppb4 at pci0 dev 10 function 0 "Intel X58 PCIE" rev 0x13
pci5 at ppb4 bus 4
"Intel X58 Misc" rev 0x13 at pci0 dev 20 function 0 not configured
"Intel X58 GPIO" rev 0x13 at pci0 dev 20 function 1 not configured
"Intel X58 RAS" rev 0x13 at pci0 dev 20 function 2 not configured
uhci0 at pci0 dev 26 function 0 "Intel 82801JI USB" rev 0x00: apic 1 int 16
(irq 10)
ehci0 at pci0 dev 26 function 7 "Intel 82801JI USB" rev 0x00: apic 1 int 18
(irq 15)
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Intel EHCI root hub" rev 2.00/1.00 addr 1
ppb5 at pci0 dev 28 function 0 "Intel 82801JI PCIE" rev 0x00: apic 1 int 16
(irq 10)
pci6 at ppb5 bus 3
ppb6 at pci0 dev 28 function 4 "Intel 82801JI PCIE" rev 0x00: apic 1 int 16
(irq 10)
pci7 at ppb6 bus 2
vga1 at pci7 dev 0 function 0 "Matrox MGA G200e (ServerEngines)" rev 0x02
wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation)
wsdisplay0: screen 1-5 added (80x25, vt100 emulation)
uhci1 at pci0 dev 29 function 0 "Intel 82801JI USB" rev 0x00: apic 1 int 23
(irq 14)
uhci2 at pci0 dev 29 function 1 "Intel 82801JI USB" rev 0x00: apic 1 int 19
(irq 11)
uhci3 at pci0 dev 29 function 2 "Intel 82801JI USB" rev 0x00: apic 1 int 18
(irq 15)
ehci1 at pci0 dev 29 function 7 "Intel 82801JI USB" rev 0x00: apic 1 int 23
(irq 14)
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 "Intel EHCI root hub" rev 2.00/1.00 addr 1
ppb7 at pci0 dev 30 function 0 "Intel 82801BA Hub-to-PCI" rev 0x90
pci8 at ppb7 bus 1
pcib0 at pci0 dev 31 function 0 "Intel 82801JIR LPC" rev 0x00
ahci0 at pci0 dev 31 function 2 "Intel 82801JI AHCI" rev 0x00: apic 1 int 19
(irq 11), AHCI 1.2
scsibus0 at ahci0: 32 targets
sd0 at scsibus0 targ 0 lun 0: <ATA, VB0160EAVEQ, HPG0> SCSI3 0/direct fixed
sd0: 152627MB, 512 bytes/sec, 312581808 sec total
usb2 at uhci0: USB revision 1.0
uhub2 at usb2 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb3 at uhci1: USB revision 1.0
uhub3 at usb3 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb4 at uhci2: USB revision 1.0
uhub4 at usb4 "Intel UHCI root hub" rev 1.00/1.00 addr 1
usb5 at uhci3: USB revision 1.0
uhub5 at usb5 "Intel UHCI root hub" rev 1.00/1.00 addr 1
isa0 at pcib0
isadma0 at isa0
com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
com0: console
pckbc0 at isa0 port 0x60/5
pckbd0 at pckbc0 (kbd slot)
pckbc0: using irq 1 for kbd slot
wskbd0 at pckbd0: console keyboard, using wsdisplay0
pms0 at pckbc0 (aux slot)
pckbc0: using irq 12 for aux slot
wsmouse0 at pms0 mux 0
pcppi0 at isa0 port 0x61
spkr0 at pcppi0
npx0 at isa0 port 0xf0/16: reported by CPUID; using exception 16
mtrr: Pentium Pro MTRR support
uhidev0 at uhub2 port 1 configuration 1 interface 0 "ServerEngines SE USB
Device" rev 1.10/0.01 addr 2
uhidev0: iclass 3/1
ukbd0 at uhidev0: 8 modifier keys, 6 key codes
wskbd1 at ukbd0 mux 1
wskbd1: connecting to wsdisplay0
uhidev1 at uhub2 port 1 configuration 1 interface 1 "ServerEngines SE USB
Device" rev 1.10/0.01 addr 2
uhidev1: iclass 3/1
ums0 at uhidev1: 8 buttons, Z dir
wsmouse1 at ums0 mux 0
vscsi0 at root
scsibus1 at vscsi0: 256 targets
softraid0 at root
root on sd0a swap on sd0b dump on sd0b
Index: arch/alpha/alpha/interrupt.c
===================================================================
RCS file: /cvs/src/sys/arch/alpha/alpha/interrupt.c,v
retrieving revision 1.29
diff -u -p -r1.29 interrupt.c
--- arch/alpha/alpha/interrupt.c 19 Apr 2009 19:13:57 -0000 1.29
+++ arch/alpha/alpha/interrupt.c 5 Nov 2010 15:50:38 -0000
@@ -88,26 +88,6 @@
#include <sys/device.h>
#endif
-#include <net/netisr.h>
-#include <net/if.h>
-
-#ifdef INET
-#include <netinet/in.h>
-#include <netinet/if_ether.h>
-#include <netinet/ip_var.h>
-#endif
-
-#ifdef INET6
-#ifndef INET
-#include <netinet/in.h>
-#endif
-#include <netinet/ip6.h>
-#include <netinet6/ip6_var.h>
-#endif
-
-#include "ppp.h"
-#include "bridge.h"
-
#include "apecs.h"
#include "cia.h"
#include "lca.h"
@@ -119,8 +99,6 @@ extern struct evcount clk_count;
struct scbvec scb_iovectab[SCB_VECTOIDX(SCB_SIZE - SCB_IOVECBASE)];
-void netintr(void);
-
void scb_stray(void *, u_long);
void
@@ -480,33 +458,8 @@ badaddr_read(void *addr, size_t size, vo
#endif /* NAPECS > 0 || NCIA > 0 || NLCA > 0 || NTCASIC > 0 */
-int netisr;
-
-void
-netintr()
-{
- int n;
-
- while ((n = netisr) != 0) {
- atomic_clearbits_int(&netisr, n);
-
-#define DONETISR(bit, fn)
\
- do { \
- if (n & (1 << (bit))) \
- fn(); \
- } while (0)
-
-#include <net/netisr_dispatch.h>
-
-#undef DONETISR
- }
-}
-
struct alpha_soft_intr alpha_soft_intrs[SI_NSOFT];
-/* XXX For legacy software interrupts. */
-struct alpha_soft_intrhand *softnet_intrhand;
-
/*
* softintr_init:
*
@@ -524,10 +477,6 @@ softintr_init()
mtx_init(&asi->softintr_mtx, IPL_HIGH);
asi->softintr_siq = i;
}
-
- /* XXX Establish legacy software interrupt handlers. */
- softnet_intrhand = softintr_establish(IPL_SOFTNET,
- (void (*)(void *))netintr, NULL);
}
/*
Index: arch/alpha/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/alpha/include/intr.h,v
retrieving revision 1.36
diff -u -p -r1.36 intr.h
--- arch/alpha/include/intr.h 31 May 2010 21:39:55 -0000 1.36
+++ arch/alpha/include/intr.h 5 Nov 2010 15:50:38 -0000
@@ -264,11 +264,6 @@ void *softintr_establish(int, void (*)(v
void softintr_init(void);
void softintr_schedule(void *);
-/* XXX For legacy software interrupts. */
-extern struct alpha_soft_intrhand *softnet_intrhand;
-
-#define setsoftnet() softintr_schedule(softnet_intrhand)
-
struct alpha_shared_intr *alpha_shared_intr_alloc(unsigned int);
int alpha_shared_intr_dispatch(struct alpha_shared_intr *,
unsigned int);
Index: arch/amd64/amd64/vector.S
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/vector.S,v
retrieving revision 1.26
diff -u -p -r1.26 vector.S
--- arch/amd64/amd64/vector.S 28 Sep 2010 03:53:14 -0000 1.26
+++ arch/amd64/amd64/vector.S 5 Nov 2010 15:50:38 -0000
@@ -78,8 +78,6 @@
#include <machine/intr.h>
#include <machine/psl.h>
-#include <net/netisr.h>
-
#include "ioapic.h"
#include "lapic.h"
#include "assym.h"
@@ -801,10 +799,6 @@ _C_LABEL(ioapic_level_stubs):
/*
* Soft interrupt handlers
*/
- .globl _C_LABEL(netisr)
-_C_LABEL(netisr):
- .word 0
-
.text
IDTVEC(softtty)
movl $IPL_SOFTTTY, CPUVAR(ILEVEL)
@@ -830,19 +824,6 @@ IDTVEC(softnet)
call _C_LABEL(x86_softintlock)
#endif
movq CPUVAR(ISOURCES) + SIR_NET * 8, %r12
-
- xorq %r12,%r12
- xchgl _C_LABEL(netisr),%r12d
-
- /* XXX Do the legacy netisrs here for now. */
-#define DONETISR(s, c) \
- .globl _C_LABEL(c) ;\
- testl $(1 << s),%r12d ;\
- jz 1f ;\
- call _C_LABEL(c) ;\
-1:
-#include <net/netisr_dispatch.h>
-
movl $X86_SOFTINTR_SOFTNET,%edi
call _C_LABEL(softintr_dispatch)
#ifdef MULTIPROCESSOR
Index: arch/amd64/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/amd64/include/intr.h,v
retrieving revision 1.19
diff -u -p -r1.19 intr.h
--- arch/amd64/include/intr.h 31 May 2010 21:39:56 -0000 1.19
+++ arch/amd64/include/intr.h 5 Nov 2010 15:50:38 -0000
@@ -172,11 +172,6 @@ void splassert_check(int, const char *);
#define splsoftassert(wantipl) do { /* nada */ } while (0)
#endif
-/*
- * XXX
- */
-#define setsoftnet() softintr(SIR_NET)
-
#define IPLSHIFT 4 /* The upper nibble of vectors is the
IPL. */
#define IPL(level) ((level) >> IPLSHIFT) /* Extract the IPL. */
Index: arch/arm/arm/softintr.c
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/softintr.c,v
retrieving revision 1.6
diff -u -p -r1.6 softintr.c
--- arch/arm/arm/softintr.c 19 Apr 2009 18:54:06 -0000 1.6
+++ arch/arm/arm/softintr.c 5 Nov 2010 15:50:38 -0000
@@ -39,9 +39,6 @@
#include <sys/param.h>
#include <sys/malloc.h>
-/* XXX Network interrupts should be converted to new softintrs. */
-#include <net/netisr.h>
-
#include <uvm/uvm_extern.h>
#include <machine/atomic.h>
@@ -49,10 +46,6 @@
struct soft_intrq soft_intrq[SI_NQUEUES];
-struct soft_intrhand *softnet_intrhand;
-
-void netintr(void);
-
/*
* softintr_init:
*
@@ -70,12 +63,6 @@ softintr_init(void)
mtx_init(&siq->siq_mtx, IPL_HIGH);
siq->siq_si = i;
}
-
- /* XXX Establish legacy software interrupt handlers. */
- softnet_intrhand = softintr_establish(IPL_SOFTNET,
- (void (*)(void *))netintr, NULL);
-
- assert(softnet_intrhand != NULL);
}
/*
@@ -171,26 +158,4 @@ softintr_disestablish(void *arg)
mtx_leave(&siq->siq_mtx);
free(sih, M_DEVBUF);
-}
-
-int netisr;
-
-void
-netintr(void)
-{
- int n;
-
- while ((n = netisr) != 0) {
- atomic_clearbits_int(&netisr, n);
-
-#define DONETISR(bit, fn)
\
- do { \
- if (n & (1 << (bit))) \
- fn(); \
- } while (/*CONSTCOND*/0)
-
-#include <net/netisr_dispatch.h>
-
-#undef DONETISR
- }
}
Index: arch/arm/include/softintr.h
===================================================================
RCS file: /cvs/src/sys/arch/arm/include/softintr.h,v
retrieving revision 1.4
diff -u -p -r1.4 softintr.h
--- arch/arm/include/softintr.h 19 Apr 2009 18:54:06 -0000 1.4
+++ arch/arm/include/softintr.h 5 Nov 2010 15:50:38 -0000
@@ -91,11 +91,6 @@ do {
\
mtx_leave(&__siq->siq_mtx); \
} while (/*CONSTCOND*/0)
-/* XXX For legacy software interrupts. */
-extern struct soft_intrhand *softnet_intrhand;
-
-#define setsoftnet() softintr_schedule(softnet_intrhand)
-
#endif /* _KERNEL */
#endif /* _ARM_SOFTINTR_H_ */
Index: arch/hppa/hppa/intr.c
===================================================================
RCS file: /cvs/src/sys/arch/hppa/hppa/intr.c,v
retrieving revision 1.35
diff -u -p -r1.35 intr.c
--- arch/hppa/hppa/intr.c 20 Sep 2010 06:33:47 -0000 1.35
+++ arch/hppa/hppa/intr.c 5 Nov 2010 15:50:38 -0000
@@ -33,17 +33,12 @@
#include <sys/evcount.h>
#include <sys/malloc.h>
-#include <net/netisr.h>
-
#include <uvm/uvm_extern.h> /* for uvmexp */
#include <machine/autoconf.h>
#include <machine/frame.h>
#include <machine/reg.h>
-void softnet(void);
-void softtty(void);
-
struct hppa_iv {
char pri;
char irq;
@@ -64,7 +59,7 @@ struct hppa_iv intr_store[8*2*CPU_NINTS]
*intr_more = intr_store, *intr_list;
struct hppa_iv intr_table[CPU_NINTS] __attribute__ ((aligned(32))) = {
{ IPL_SOFTCLOCK, 0, HPPA_IV_SOFT, 0, 0, NULL },
- { IPL_SOFTNET , 0, HPPA_IV_SOFT, 0, 0, (int (*)(void *))&softnet },
+ { IPL_SOFTNET , 0, HPPA_IV_SOFT, 0, 0, NULL },
{ 0 },
{ 0 },
{ IPL_SOFTTTY , 0, HPPA_IV_SOFT, 0, 0, NULL }
@@ -88,18 +83,6 @@ splassert_check(int wantipl, const char
splassert_fail(wantipl, ci->ci_cpl, func);
}
#endif
-
-void
-softnet(void)
-{
- int ni;
-
- /* use atomic "load & clear" */
- __asm __volatile(
- "ldcws 0(%2), %0": "=&r" (ni), "+m" (netisr): "r" (&netisr));
-#define DONETISR(m,c) if (ni & (1 << (m))) c()
-#include <net/netisr_dispatch.h>
-}
void
cpu_intr_init(void)
Index: arch/hppa/hppa/locore.S
===================================================================
RCS file: /cvs/src/sys/arch/hppa/hppa/locore.S,v
retrieving revision 1.180
diff -u -p -r1.180 locore.S
--- arch/hppa/hppa/locore.S 28 Nov 2010 20:09:14 -0000 1.180
+++ arch/hppa/hppa/locore.S 30 Nov 2010 16:29:02 -0000
@@ -102,13 +102,6 @@
.data
- .export netisr, data
- .align 16
-netisr
- .word 0
- .size netisr, .-netisr
- .align 16
-
BSS(pdc_stack, 4) /* temp stack for PDC call */
BSS(emrg_stack, 4) /* stack for HPMC/TOC/PWRF */
Index: arch/hppa/hppa/trap.c
===================================================================
RCS file: /cvs/src/sys/arch/hppa/hppa/trap.c,v
retrieving revision 1.111
diff -u -p -r1.111 trap.c
--- arch/hppa/hppa/trap.c 27 Nov 2010 19:57:23 -0000 1.111
+++ arch/hppa/hppa/trap.c 30 Nov 2010 16:29:02 -0000
@@ -36,8 +36,6 @@
#include <sys/signalvar.h>
#include <sys/user.h>
-#include <net/netisr.h>
-
#include "systrace.h"
#include <dev/systrace.h>
Index: arch/hppa/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/hppa/include/intr.h,v
retrieving revision 1.34
diff -u -p -r1.34 intr.h
--- arch/hppa/include/intr.h 2 Jul 2010 00:00:45 -0000 1.34
+++ arch/hppa/include/intr.h 5 Nov 2010 15:50:38 -0000
@@ -156,7 +156,6 @@ int hppa_ipi_send(struct cpu_info *, u_
#endif
#define setsoftast(p) (p->p_md.md_astpending = 1)
-#define setsoftnet() softintr(1 << (IPL_SOFTNET - 1))
void *softintr_establish(int, void (*)(void *), void *);
void softintr_disestablish(void *);
Index: arch/hppa64/hppa64/locore.S
===================================================================
RCS file: /cvs/src/sys/arch/hppa64/hppa64/locore.S,v
retrieving revision 1.10
diff -u -p -r1.10 locore.S
--- arch/hppa64/hppa64/locore.S 18 Aug 2010 21:01:14 -0000 1.10
+++ arch/hppa64/hppa64/locore.S 5 Nov 2010 15:50:38 -0000
@@ -44,10 +44,6 @@
.data
- .export netisr, data
- .align 16
-netisr
- .word 0
.align 16
$kpsl
.word PSL_W | PSL_Q | PSL_P | PSL_C | PSL_D | PSL_S | PSL_O
Index: arch/hppa64/hppa64/trap.c
===================================================================
RCS file: /cvs/src/sys/arch/hppa64/hppa64/trap.c,v
retrieving revision 1.11
diff -u -p -r1.11 trap.c
--- arch/hppa64/hppa64/trap.c 27 Nov 2010 19:57:23 -0000 1.11
+++ arch/hppa64/hppa64/trap.c 30 Nov 2010 16:29:04 -0000
@@ -27,8 +27,6 @@
#include <sys/signalvar.h>
#include <sys/user.h>
-#include <net/netisr.h>
-
#include "systrace.h"
#include <dev/systrace.h>
Index: arch/hppa64/include/cpu.h
===================================================================
RCS file: /cvs/src/sys/arch/hppa64/include/cpu.h,v
retrieving revision 1.18
diff -u -p -r1.18 cpu.h
--- arch/hppa64/include/cpu.h 28 Sep 2010 20:27:54 -0000 1.18
+++ arch/hppa64/include/cpu.h 5 Nov 2010 15:50:38 -0000
@@ -110,9 +110,6 @@
#define splx(c) spllower(c)
#define setsoftast() (astpending = 1)
-#define setsoftclock() /* TODO */
-#define setsoftnet() /* TODO */
-#define setsofttty() /* TODO */
#ifndef _LOCORE
#include <sys/time.h>
Index: arch/i386/i386/apicvec.s
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/apicvec.s,v
retrieving revision 1.21
diff -u -p -r1.21 apicvec.s
--- arch/i386/i386/apicvec.s 11 Jan 2010 23:09:52 -0000 1.21
+++ arch/i386/i386/apicvec.s 5 Nov 2010 15:50:38 -0000
@@ -207,13 +207,6 @@ XINTR(softclock):
decl CPUVAR(IDEPTH)
jmp _C_LABEL(Xdoreti)
-#define DONETISR(s, c) \
- .globl _C_LABEL(c) ;\
- testl $(1 << s),%edi ;\
- jz 1f ;\
- call _C_LABEL(c) ;\
-1:
-
XINTR(softnet):
pushl $0
pushl $T_ASTFLT
@@ -228,11 +221,6 @@ XINTR(softnet):
#ifdef MULTIPROCESSOR
call _C_LABEL(i386_softintlock)
#endif
- xorl %edi,%edi
- xchgl _C_LABEL(netisr),%edi
-
-#include <net/netisr_dispatch.h>
-
pushl $I386_SOFTINTR_SOFTNET
call _C_LABEL(softintr_dispatch)
addl $4,%esp
Index: arch/i386/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/i386/include/intr.h,v
retrieving revision 1.39
diff -u -p -r1.39 intr.h
--- arch/i386/include/intr.h 13 Aug 2009 13:24:48 -0000 1.39
+++ arch/i386/include/intr.h 5 Nov 2010 15:50:38 -0000
@@ -126,9 +126,6 @@ void splassert_check(int, const char *);
#define spllock() splhigh()
#define spl0() spllower(IPL_NONE)
-#define setsoftnet() softintr(SIR_NET)
-#define setsofttty() softintr(SIR_TTY)
-
#include <machine/pic.h>
struct cpu_info;
Index: arch/i386/isa/icu.s
===================================================================
RCS file: /cvs/src/sys/arch/i386/isa/icu.s,v
retrieving revision 1.30
diff -u -p -r1.30 icu.s
--- arch/i386/isa/icu.s 9 May 2010 12:03:16 -0000 1.30
+++ arch/i386/isa/icu.s 5 Nov 2010 15:50:38 -0000
@@ -30,14 +30,10 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <net/netisr.h>
-
.data
- .globl _C_LABEL(imen),_C_LABEL(netisr)
+ .globl _C_LABEL(imen)
_C_LABEL(imen):
.long 0xffff # interrupt mask enable (all off)
-_C_LABEL(netisr):
- .long 0 # scheduling bits for network
.text
/*
@@ -136,13 +132,6 @@ IDTVEC(softtty)
#endif
jmp *%esi
-#define DONETISR(s, c) \
- .globl _C_LABEL(c) ;\
- testl $(1 << s),%edi ;\
- jz 1f ;\
- call _C_LABEL(c) ;\
-1:
-
IDTVEC(softnet)
movl $IPL_SOFTNET,%eax
movl %eax,CPL
@@ -150,11 +139,6 @@ IDTVEC(softnet)
#ifdef MULTIPROCESSOR
call _C_LABEL(i386_softintlock)
#endif
- xorl %edi,%edi
- xchgl _C_LABEL(netisr),%edi
-
-#include <net/netisr_dispatch.h>
-
pushl $I386_SOFTINTR_SOFTNET
call _C_LABEL(softintr_dispatch)
addl $4,%esp
Index: arch/loongson/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/loongson/include/intr.h,v
retrieving revision 1.2
diff -u -p -r1.2 intr.h
--- arch/loongson/include/intr.h 23 Apr 2010 03:50:22 -0000 1.2
+++ arch/loongson/include/intr.h 5 Nov 2010 15:50:38 -0000
@@ -106,11 +106,6 @@ void *softintr_establish(int, void (*)(v
void softintr_init(void);
void softintr_schedule(void *);
-/* XXX For legacy software interrupts. */
-extern struct soft_intrhand *softnet_intrhand;
-
-#define setsoftnet() softintr_schedule(softnet_intrhand)
-
#define splsoft() splraise(IPL_SOFTINT)
#define splbio() splraise(IPL_BIO)
#define splnet() splraise(IPL_NET)
Index: arch/luna88k/luna88k/isr.c
===================================================================
RCS file: /cvs/src/sys/arch/luna88k/luna88k/isr.c,v
retrieving revision 1.8
diff -u -p -r1.8 isr.c
--- arch/luna88k/luna88k/isr.c 20 Sep 2010 06:33:47 -0000 1.8
+++ arch/luna88k/luna88k/isr.c 5 Nov 2010 15:50:38 -0000
@@ -42,8 +42,6 @@
#include <uvm/uvm_extern.h>
-#include <net/netisr.h>
-
#include <machine/cpu.h>
#include <luna88k/luna88k/isr.h>
Index: arch/m68k/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/m68k/include/intr.h,v
retrieving revision 1.1
diff -u -p -r1.1 intr.h
--- arch/m68k/include/intr.h 15 Mar 2009 20:40:25 -0000 1.1
+++ arch/m68k/include/intr.h 5 Nov 2010 15:50:38 -0000
@@ -101,11 +101,6 @@ void softintr_schedule(void *);
extern int softpending;
-/* XXX For legacy software interrupts. */
-extern struct soft_intrhand *softnet_intrhand;
-
-#define setsoftnet() softintr_schedule(softnet_intrhand)
-
#endif /* _LOCORE */
#endif /* _KERNEL */
Index: arch/m68k/m68k/softintr.c
===================================================================
RCS file: /cvs/src/sys/arch/m68k/m68k/softintr.c,v
retrieving revision 1.1
diff -u -p -r1.1 softintr.c
--- arch/m68k/m68k/softintr.c 15 Mar 2009 20:40:25 -0000 1.1
+++ arch/m68k/m68k/softintr.c 5 Nov 2010 15:50:38 -0000
@@ -39,9 +39,6 @@
#include <sys/param.h>
#include <sys/malloc.h>
-/* XXX Network interrupts should be converted to new softintrs. */
-#include <net/netisr.h>
-
#include <uvm/uvm_extern.h>
#include <machine/atomic.h>
@@ -49,10 +46,6 @@
struct soft_intrq soft_intrq[SI_NQUEUES];
-struct soft_intrhand *softnet_intrhand;
-
-void netintr(void);
-
/*
* Initialize the software interrupt system.
*/
@@ -68,10 +61,6 @@ softintr_init(void)
siq->siq_si = i;
mtx_init(&siq->siq_mtx, IPL_HIGH);
}
-
- /* XXX Establish legacy software interrupt handlers. */
- softnet_intrhand = softintr_establish(IPL_SOFTNET,
- (void (*)(void *))netintr, NULL);
}
/*
@@ -176,23 +165,4 @@ softintr_schedule(void *arg)
atomic_setbits_int(&softpending, 1 << siq->siq_si);
}
mtx_leave(&siq->siq_mtx);
-}
-
-int netisr;
-
-void
-netintr(void)
-{
- int n;
-
- while ((n = netisr) != 0) {
- atomic_clearbits_int(&netisr, n);
-#define DONETISR(bit, fn)
\
- do { \
- if (n & (1 << (bit))) \
- fn(); \
- } while (0)
-#include <net/netisr_dispatch.h>
-#undef DONETISR
- }
}
Index: arch/m88k/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/m88k/include/intr.h,v
retrieving revision 1.11
diff -u -p -r1.11 intr.h
--- arch/m88k/include/intr.h 15 Mar 2009 20:39:53 -0000 1.11
+++ arch/m88k/include/intr.h 5 Nov 2010 15:50:38 -0000
@@ -150,11 +150,6 @@ void softintr_schedule(void *);
extern int softpending;
-/* XXX For legacy software interrupts. */
-extern struct soft_intrhand *softnet_intrhand;
-
-#define setsoftnet() softintr_schedule(softnet_intrhand)
-
#endif /* _LOCORE */
#endif /* _KERNEL */
Index: arch/m88k/m88k/softintr.c
===================================================================
RCS file: /cvs/src/sys/arch/m88k/m88k/softintr.c,v
retrieving revision 1.1
diff -u -p -r1.1 softintr.c
--- arch/m88k/m88k/softintr.c 15 Mar 2009 20:39:53 -0000 1.1
+++ arch/m88k/m88k/softintr.c 5 Nov 2010 15:50:38 -0000
@@ -39,9 +39,6 @@
#include <sys/param.h>
#include <sys/malloc.h>
-/* XXX Network interrupts should be converted to new softintrs. */
-#include <net/netisr.h>
-
#include <uvm/uvm_extern.h>
#include <machine/atomic.h>
@@ -49,10 +46,6 @@
struct soft_intrq soft_intrq[SI_NQUEUES];
-struct soft_intrhand *softnet_intrhand;
-
-void netintr(void);
-
/*
* Initialize the software interrupt system.
*/
@@ -68,10 +61,6 @@ softintr_init(void)
siq->siq_si = i;
mtx_init(&siq->siq_mtx, IPL_HIGH);
}
-
- /* XXX Establish legacy software interrupt handlers. */
- softnet_intrhand = softintr_establish(IPL_SOFTNET,
- (void (*)(void *))netintr, NULL);
}
/*
@@ -176,22 +165,4 @@ softintr_schedule(void *arg)
atomic_setbits_int(&softpending, 1 << siq->siq_si);
}
mtx_leave(&siq->siq_mtx);
-}
-
-int netisr;
-
-void
-netintr(void)
-{
- int n;
-
- while ((n = atomic_clear_int(&netisr)) != 0) {
-#define DONETISR(bit, fn)
\
- do { \
- if (n & (1 << (bit))) \
- fn(); \
- } while (0)
-#include <net/netisr_dispatch.h>
-#undef DONETISR
- }
}
Index: arch/mips64/mips64/softintr.c
===================================================================
RCS file: /cvs/src/sys/arch/mips64/mips64/softintr.c,v
retrieving revision 1.11
diff -u -p -r1.11 softintr.c
--- arch/mips64/mips64/softintr.c 18 Jan 2010 17:00:28 -0000 1.11
+++ arch/mips64/mips64/softintr.c 5 Nov 2010 15:50:38 -0000
@@ -39,9 +39,6 @@
#include <sys/param.h>
#include <sys/malloc.h>
-/* XXX Network interrupts should be converted to new softintrs. */
-#include <net/netisr.h>
-
#include <uvm/uvm_extern.h>
#include <machine/atomic.h>
@@ -49,8 +46,6 @@
struct soft_intrq soft_intrq[SI_NQUEUES];
-struct soft_intrhand *softnet_intrhand;
-
void netintr(void);
/*
@@ -68,10 +63,6 @@ softintr_init(void)
siq->siq_si = i;
mtx_init(&siq->siq_mtx, IPL_HIGH);
}
-
- /* XXX Establish legacy software interrupt handlers. */
- softnet_intrhand = softintr_establish(IPL_SOFTNET,
- (void (*)(void *))netintr, NULL);
}
/*
@@ -178,25 +169,6 @@ softintr_schedule(void *arg)
atomic_setbits_int(&ci->ci_softpending, SINTMASK(siq->siq_si));
}
mtx_leave(&siq->siq_mtx);
-}
-
-int netisr;
-
-void
-netintr(void)
-{
- int n;
-
- while ((n = netisr) != 0) {
- atomic_clearbits_int(&netisr, n);
-#define DONETISR(bit, fn)
\
- do { \
- if (n & (1 << (bit))) \
- fn(); \
- } while (0)
-#include <net/netisr_dispatch.h>
-#undef DONETISR
- }
}
void
Index: arch/mvmeppc/mvmeppc/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/mvmeppc/mvmeppc/machdep.c,v
retrieving revision 1.63
diff -u -p -r1.63 machdep.c
--- arch/mvmeppc/mvmeppc/machdep.c 22 Aug 2009 02:54:50 -0000 1.63
+++ arch/mvmeppc/mvmeppc/machdep.c 5 Nov 2010 15:50:53 -0000
@@ -49,8 +49,6 @@
#include <sys/systm.h>
#include <sys/user.h>
-#include <net/netisr.h>
-
#include <machine/bat.h>
#include <machine/bugio.h>
#include <machine/pmap.h>
@@ -594,22 +592,6 @@ dumpsys()
volatile int cpl, ipending, astpending;
int imask[IPL_NUM];
-int netisr;
-
-/*
- * Soft networking interrupts.
- */
-void
-softnet(isr)
- int isr;
-{
-#define DONETISR(flag, func) \
- if (isr & (1 << (flag))) \
- (func)();
-
-#include <net/netisr_dispatch.h>
-#undef DONETISR
-}
int
lcsplx(ipl)
Index: arch/powerpc/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/powerpc/include/intr.h,v
retrieving revision 1.44
diff -u -p -r1.44 intr.h
--- arch/powerpc/include/intr.h 23 Apr 2010 03:50:22 -0000 1.44
+++ arch/powerpc/include/intr.h 5 Nov 2010 15:50:53 -0000
@@ -115,11 +115,6 @@ void *softintr_establish(int, void (*)(v
void softintr_init(void);
void softintr_schedule(void *);
-/* XXX For legacy software interrupts. */
-extern struct soft_intrhand *softnet_intrhand;
-
-#define setsoftnet() softintr_schedule(softnet_intrhand)
-
#define SINT_CLOCK SINTMASK(SI_SOFTCLOCK)
#define SINT_NET SINTMASK(SI_SOFTNET)
#define SINT_TTY SINTMASK(SI_SOFTTTY)
Index: arch/powerpc/powerpc/softintr.c
===================================================================
RCS file: /cvs/src/sys/arch/powerpc/powerpc/softintr.c,v
retrieving revision 1.2
diff -u -p -r1.2 softintr.c
--- arch/powerpc/powerpc/softintr.c 8 Nov 2009 21:05:18 -0000 1.2
+++ arch/powerpc/powerpc/softintr.c 5 Nov 2010 15:50:53 -0000
@@ -39,9 +39,6 @@
#include <sys/param.h>
#include <sys/malloc.h>
-/* XXX Network interrupts should be converted to new softintrs. */
-#include <net/netisr.h>
-
#include <uvm/uvm_extern.h>
#include <machine/atomic.h>
@@ -51,8 +48,6 @@ struct soft_intrq soft_intrq[SI_NQUEUES]
struct soft_intrhand *softnet_intrhand;
-void netintr(void);
-
/*
* Initialize the software interrupt system.
*/
@@ -68,10 +63,6 @@ softintr_init(void)
siq->siq_si = i;
mtx_init(&siq->siq_mtx, IPL_HIGH);
}
-
- /* XXX Establish legacy software interrupt handlers. */
- softnet_intrhand = softintr_establish(IPL_SOFTNET,
- (void (*)(void *))netintr, NULL);
}
/*
@@ -182,25 +173,6 @@ softintr_schedule(void *arg)
atomic_setbits_int(&ci->ci_ipending, SINTMASK(siq->siq_si));
}
mtx_leave(&siq->siq_mtx);
-}
-
-int netisr;
-
-void
-netintr(void)
-{
- int n;
-
- while ((n = netisr) != 0) {
- atomic_clearbits_int(&netisr, n);
-#define DONETISR(bit, fn)
\
- do { \
- if (n & (1 << (bit))) \
- fn(); \
- } while (0)
-#include <net/netisr_dispatch.h>
-#undef DONETISR
- }
}
#if 0
Index: arch/sgi/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/sgi/include/intr.h,v
retrieving revision 1.41
diff -u -p -r1.41 intr.h
--- arch/sgi/include/intr.h 18 Jan 2010 16:59:23 -0000 1.41
+++ arch/sgi/include/intr.h 5 Nov 2010 15:50:53 -0000
@@ -107,11 +107,6 @@ void *softintr_establish(int, void (*)(v
void softintr_init(void);
void softintr_schedule(void *);
-/* XXX For legacy software interrupts. */
-extern struct soft_intrhand *softnet_intrhand;
-
-#define setsoftnet() softintr_schedule(softnet_intrhand)
-
#define splsoft() splraise(IPL_SOFTINT)
#define splbio() splraise(IPL_BIO)
#define splnet() splraise(IPL_NET)
Index: arch/sh/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/sh/include/intr.h,v
retrieving revision 1.7
diff -u -p -r1.7 intr.h
--- arch/sh/include/intr.h 19 Apr 2009 18:54:06 -0000 1.7
+++ arch/sh/include/intr.h 5 Nov 2010 15:50:53 -0000
@@ -114,11 +114,6 @@ void *softintr_establish(int, void (*)(v
void softintr_init(void);
void softintr_schedule(void *);
-/* XXX For legacy software interrupts. */
-extern struct sh_soft_intrhand *softnet_intrhand;
-
-#define setsoftnet() softintr_schedule(softnet_intrhand)
-
#endif /* _KERNEL */
#endif /* !_SH_INTR_H_ */
Index: arch/sh/sh/interrupt.c
===================================================================
RCS file: /cvs/src/sys/arch/sh/sh/interrupt.c,v
retrieving revision 1.11
diff -u -p -r1.11 interrupt.c
--- arch/sh/sh/interrupt.c 20 Sep 2010 06:33:47 -0000 1.11
+++ arch/sh/sh/interrupt.c 5 Nov 2010 15:50:53 -0000
@@ -35,8 +35,6 @@
#include <uvm/uvm_extern.h> /* uvmexp.intrs */
-#include <net/netisr.h>
-
#include <sh/clock.h>
#include <sh/trap.h>
#include <sh/intcreg.h>
@@ -61,8 +59,6 @@ void tmu2_oneshot(void);
int tmu2_intr(void *);
void setsoft(int);
-int netisr;
-
/*
* EVTCODE to intc_intrhand mapper.
* max #76 is SH4_INTEVT_TMU4 (0xb80)
@@ -75,7 +71,6 @@ struct intc_intrhand __intc_intrhand[_IN
};
struct sh_soft_intr sh_soft_intrs[_IPL_NSOFT];
-struct sh_soft_intrhand *softnet_intrhand;
/*
* SH INTC support.
@@ -588,11 +583,6 @@ softintr_init(void)
asi->softintr_ipl = IPL_SOFT + i;
}
- /* XXX Establish legacy soft interrupt handlers. */
- softnet_intrhand = softintr_establish(IPL_SOFTNET,
- (void (*)(void *))netintr, NULL);
- KDASSERT(softnet_intrhand != NULL);
-
intc_intr_establish(SH_INTEVT_TMU1_TUNI1, IST_LEVEL, IPL_SOFT,
tmu1_intr, NULL, "tmu1");
intc_intr_establish(SH_INTEVT_TMU2_TUNI2, IST_LEVEL, IPL_SOFTNET,
@@ -687,29 +677,6 @@ void softintr_schedule(void *arg)
setsoft(si->softintr_ipl);
}
mtx_leave(&si->softintr_lock);
-}
-
-/*
- * Software (low priority) network interrupt. i.e. softnet().
- */
-void
-netintr(void)
-{
- int n;
-
- while ((n = netisr) != 0) {
- atomic_clearbits_int(&netisr, n);
-
-#define DONETISR(bit, fn)
\
- do { \
- if (n & (1 << bit)) \
- fn(); \
- } while (/*CONSTCOND*/0)
-
-#include <net/netisr_dispatch.h>
-
-#undef DONETISR
- }
}
/*
Index: arch/sparc/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/sparc/include/intr.h,v
retrieving revision 1.1
diff -u -p -r1.1 intr.h
--- arch/sparc/include/intr.h 10 Apr 2009 20:53:54 -0000 1.1
+++ arch/sparc/include/intr.h 5 Nov 2010 15:50:53 -0000
@@ -94,9 +94,5 @@ void softintr_disestablish(void *);
void *softintr_establish(int, void (*)(void *), void *);
void softintr_schedule(void *);
-/* XXX legacy software interrupts */
-extern void *softnet_ih;
-#define setsoftnet() softintr_schedule(softnet_ih)
-
#endif /* _KERNEL */
#endif /* _SPARC_INTR_H_ */
Index: arch/sparc/sparc/intr.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc/sparc/intr.c,v
retrieving revision 1.36
diff -u -p -r1.36 intr.c
--- arch/sparc/sparc/intr.c 28 Sep 2010 18:52:00 -0000 1.36
+++ arch/sparc/sparc/intr.c 5 Nov 2010 15:56:59 -0000
@@ -51,9 +51,6 @@
#include <dev/cons.h>
-#include <net/netisr.h>
-#include <net/if.h>
-
#include <machine/atomic.h>
#include <machine/cpu.h>
#include <machine/ctlreg.h>
@@ -62,26 +59,11 @@
#include <sparc/sparc/cpuvar.h>
-#ifdef INET
-#include <netinet/in.h>
-#include <netinet/if_ether.h>
-#include <netinet/ip_var.h>
-#endif
-
-#ifdef INET6
-# ifndef INET
-# include <netinet/in.h>
-# endif
-#include <netinet/ip6.h>
-#include <netinet6/ip6_var.h>
-#endif
-
extern void raise(int, int);
void ih_insert(struct intrhand **, struct intrhand *);
void ih_remove(struct intrhand **, struct intrhand *);
-void softnet(void *);
void strayintr(struct clockframe *);
/*
@@ -180,8 +162,6 @@ intr_init()
evcount_attach(&level10.ih_count, "clock", &level10.ih_vec);
level14.ih_vec = level14.ih_ipl >> 8;
evcount_attach(&level14.ih_count, "prof", &level14.ih_vec);
-
- softnet_ih = softintr_establish(IPL_SOFTNET, softnet, NULL);
}
/*
@@ -554,29 +534,6 @@ softintr_schedule(void *arg)
}
}
splx(s);
-}
-
-void *softnet_ih;
-int netisr;
-
-void
-softnet(void *arg)
-{
- int n;
-
- while ((n = netisr) != 0) {
- atomic_clearbits_int(&netisr, n);
-
-#define DONETISR(bit, fn) \
- do { \
- if (n & (1 << bit)) \
- fn(); \
- } while (0)
-
-#include <net/netisr_dispatch.h>
-
-#undef DONETISR
- }
}
#ifdef DIAGNOSTIC
Index: arch/sparc64/include/cpu.h
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/include/cpu.h,v
retrieving revision 1.74
diff -u -p -r1.74 cpu.h
--- arch/sparc64/include/cpu.h 27 Nov 2010 19:41:48 -0000 1.74
+++ arch/sparc64/include/cpu.h 30 Nov 2010 16:29:22 -0000
@@ -221,8 +221,6 @@ struct clockframe {
extern void (*cpu_start_clock)(void);
-void setsoftnet(void);
-
#define aston(p) ((p)->p_md.md_astpending = 1)
/*
Index: arch/sparc64/sparc64/intr.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/sparc64/intr.c,v
retrieving revision 1.38
diff -u -p -r1.38 intr.c
--- arch/sparc64/sparc64/intr.c 27 Sep 2010 17:39:43 -0000 1.38
+++ arch/sparc64/sparc64/intr.c 5 Nov 2010 15:50:53 -0000
@@ -48,8 +48,6 @@
#include <dev/cons.h>
-#include <net/netisr.h>
-
#include <machine/atomic.h>
#include <machine/cpu.h>
#include <machine/ctlreg.h>
@@ -69,7 +67,6 @@ struct intrhand *intrlev[MAXINTNUM];
void strayintr(const struct trapframe64 *, int);
int softintr(void *);
-int softnet(void *);
int intr_list_handler(void *);
void intr_ack(struct intrhand *);
@@ -124,37 +121,6 @@ strayintr(fp, vectored)
* Network software interrupt
* Soft clock interrupt
*/
-
-int netisr;
-
-int
-softnet(fp)
- void *fp;
-{
- int n;
-
- while ((n = netisr) != 0) {
- atomic_clearbits_int(&netisr, n);
-
-#define DONETISR(bit, fn) \
- do { \
- if (n & (1 << bit)) \
- fn(); \
- } while (0)
-
-#include <net/netisr_dispatch.h>
-
-#undef DONETISR
- }
- return (1);
-}
-
-struct intrhand soft01net = { softnet, NULL, 1 };
-
-void
-setsoftnet() {
- send_softint(-1, IPL_SOFTNET, &soft01net);
-}
/*
* PCI devices can share interrupts so we need to have
Index: arch/vax/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/vax/include/intr.h,v
retrieving revision 1.12
diff -u -p -r1.12 intr.h
--- arch/vax/include/intr.h 23 Apr 2010 03:50:22 -0000 1.12
+++ arch/vax/include/intr.h 5 Nov 2010 15:50:53 -0000
@@ -155,11 +155,6 @@ void *softintr_establish(int, void (*)(v
void softintr_init(void);
void softintr_schedule(void *);
-/* XXX For legacy software interrupts. */
-extern struct soft_intrhand *softnet_intrhand;
-
-#define setsoftnet() softintr_schedule(softnet_intrhand)
-
#endif /* _LOCORE */
#endif /* _VAX_INTR_H */
Index: arch/vax/vax/locore.S
===================================================================
RCS file: /cvs/src/sys/arch/vax/vax/locore.S,v
retrieving revision 1.4
diff -u -p -r1.4 locore.S
--- arch/vax/vax/locore.S 27 Nov 2010 18:04:23 -0000 1.4
+++ arch/vax/vax/locore.S 30 Nov 2010 16:29:24 -0000
@@ -35,7 +35,6 @@
#include "assym.h"
#include <machine/asm.h>
-#include <net/netisr.h>
#define JSBENTRY(x) \
.text; _ALIGN_TEXT; .globl x; x:
@@ -278,11 +277,6 @@ JSBENTRY(sbiflt)
TRAPCALL(astintr, T_ASTFLT)
FASTINTR(softintr,softintr_dispatch)
-
- .data
- .global _netisr
-_netisr:
- .long 0 # scheduling bits for network
TRAPCALL(ddbtrap, T_KDBTRAP)
Index: arch/vax/vax/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/vax/vax/machdep.c,v
retrieving revision 1.110
diff -u -p -r1.110 machdep.c
--- arch/vax/vax/machdep.c 29 Jun 2010 18:46:34 -0000 1.110
+++ arch/vax/vax/machdep.c 5 Nov 2010 15:50:53 -0000
@@ -76,7 +76,6 @@
#include <uvm/uvm.h>
-#include <net/netisr.h>
#include <net/if.h>
#ifdef INET
Index: arch/vax/vax/softintr.c
===================================================================
RCS file: /cvs/src/sys/arch/vax/vax/softintr.c,v
retrieving revision 1.1
diff -u -p -r1.1 softintr.c
--- arch/vax/vax/softintr.c 20 Mar 2009 18:39:30 -0000 1.1
+++ arch/vax/vax/softintr.c 5 Nov 2010 15:50:53 -0000
@@ -39,9 +39,6 @@
#include <sys/param.h>
#include <sys/malloc.h>
-/* XXX Network interrupts should be converted to new softintrs. */
-#include <net/netisr.h>
-
#include <uvm/uvm_extern.h>
#include <machine/atomic.h>
@@ -170,23 +167,4 @@ softintr_schedule(void *arg)
mtpr(siq->siq_si, PR_SIRR);
}
mtx_leave(&siq->siq_mtx);
-}
-
-int netisr;
-
-void
-netintr(void)
-{
- int n;
-
- while ((n = netisr) != 0) {
- atomic_clearbits_int(&netisr, n);
-#define DONETISR(bit, fn)
\
- do { \
- if (n & (1 << (bit))) \
- fn(); \
- } while (0)
-#include <net/netisr_dispatch.h>
-#undef DONETISR
- }
}
Index: conf/files
===================================================================
RCS file: /cvs/src/sys/conf/files,v
retrieving revision 1.504
diff -u -p -r1.504 files
--- conf/files 6 Oct 2010 22:19:20 -0000 1.504
+++ conf/files 5 Nov 2010 15:50:53 -0000
@@ -807,6 +807,7 @@ file net/if_loop.c loop
file net/if_media.c ifmedia
file net/if_sl.c sl needs-count
file net/if_ppp.c ppp needs-count
+file net/netisr.c
file net/ppp_tty.c ppp
file net/bsd-comp.c ppp_bsdcomp
file net/ppp-deflate.c ppp_deflate
Index: kern/init_main.c
===================================================================
RCS file: /cvs/src/sys/kern/init_main.c,v
retrieving revision 1.171
diff -u -p -r1.171 init_main.c
--- kern/init_main.c 8 Sep 2010 14:15:56 -0000 1.171
+++ kern/init_main.c 5 Nov 2010 15:50:53 -0000
@@ -89,6 +89,7 @@
#include <net/if.h>
#include <net/raw_cb.h>
+#include <net/netisr.h>
#if defined(CRYPTO)
#include <crypto/cryptodev.h>
@@ -396,6 +397,7 @@ main(void *framep)
* until everything is ready.
*/
s = splnet();
+ netisr_init();
domaininit();
if_attachdomain();
splx(s);
Index: net/netisr.c
===================================================================
RCS file: net/netisr.c
diff -N net/netisr.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ net/netisr.c 25 Nov 2010 16:09:52 -0000
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2010 Owain G. Ainsworth <o...@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <net/netisr.h>
+
+#include <machine/intr.h>
+
+#include "bluetooth.h"
+#include "ether.h"
+#include "ppp.h"
+#include "bridge.h"
+#include "pppoe.h"
+#include "pfsync.h"
+
+void netintr(void *);
+
+int netisr;
+void *netisr_intr;
+
+void
+netintr(void *unused) /* ARGSUSED */
+{
+ int n;
+ while ((n = netisr) != 0) {
+ atomic_clearbits_int(&netisr, n);
+
+#ifdef INET
+#if NETHER > 0
+ if (n & 1 << NETISR_ARP)
+ arpintr();
+#endif
+ if (n & 1 << NETISR_IP)
+ ipintr();
+#endif
+#ifdef INET6
+ if (n & 1 << NETISR_IPV6)
+ ip6intr();
+#endif
+#ifdef MPLS
+ if (n & 1 << NETISR_MPLS)
+ mplsintr();
+#endif
+#ifdef NETATALK
+ if (n & 1 << NETISR_ATALK)
+ atintr();
+#endif
+#if NATM > 0
+ if (n & 1 << NETISR_NATM)
+ natmintr();
+#endif
+#if NPPP > 0
+ if (n & 1 << NETISR_PPP)
+ pppintr();
+#endif
+#if NBRIDGE > 0
+ if (n & 1 << NETISR_BRIDGE)
+ bridgeintr();
+#endif
+#if NPPPOE > 0
+ if (n & 1 << NETISR_PPPOE)
+ pppoeintr();
+#endif
+#if NBLUETOOTH > 0
+ if (n & 1 << NETISR_BT)
+ btintr();
+#endif
+#if NPFSYNC > 0
+ if (n & 1 << NETISR_PFSYNC)
+ pfsyncintr();
+#endif
+ if (n & 1 << NETISR_TX)
+ nettxintr();
+ }
+}
+
+void
+netisr_init(void)
+{
+ netisr_intr = softintr_establish(IPL_SOFTNET, netintr, NULL);
+ if (netisr_intr == NULL)
+ panic("can't establish softnet handler");
+}
Index: net/netisr.h
===================================================================
RCS file: /cvs/src/sys/net/netisr.h,v
retrieving revision 1.34
diff -u -p -r1.34 netisr.h
--- net/netisr.h 16 Feb 2009 00:31:25 -0000 1.34
+++ net/netisr.h 5 Nov 2010 15:50:53 -0000
@@ -41,9 +41,6 @@
* The software interrupt level for the network is higher than the software
* level for the clock (so you can enter the network in routines called
* at timeout time).
- *
- * The routine to request a network software interrupt, setsoftnet(),
- * is defined in the machine-specific include files.
*/
/*
@@ -86,11 +83,16 @@ void mplsintr(void);
void pfsyncintr(void);
#include <machine/atomic.h>
+
+extern void *netisr_intr;
#define schednetisr(anisr)
\
do { \
atomic_setbits_int(&netisr, (1 << (anisr))); \
- setsoftnet(); \
-} while (0)
+ softintr_schedule(netisr_intr);
\
+} while (/* CONSTCOND */0)
+
+void netisr_init(void);
+
#endif
#endif
Index: net/netisr_dispatch.h
===================================================================
RCS file: net/netisr_dispatch.h
diff -N net/netisr_dispatch.h
--- net/netisr_dispatch.h 16 Feb 2009 00:31:25 -0000 1.17
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,71 +0,0 @@
-/* $OpenBSD: netisr_dispatch.h,v 1.17 2009/02/16 00:31:25 dlg Exp $
*/
-/* $NetBSD: netisr_dispatch.h,v 1.2 2000/07/02 04:40:47 cgd Exp $ */
-
-/*
- * netisr_dispatch: This file is included by the
- * machine dependant softnet function. The
- * DONETISR macro should be set before including
- * this file. i.e.:
- *
- * softintr() {
- * ...do setup stuff...
- * #define DONETISR(bit, fn) do { ... } while (0)
- * #include <net/netisr_dispatch.h>
- * #undef DONETISR
- * ...do cleanup stuff.
- * }
- */
-
-#ifndef _NET_NETISR_H_
-#error <net/netisr.h> must be included before <net/netisr_dispatch.h>
-#endif
-
-#ifndef _NET_NETISR_DISPATCH_H_
-#define _NET_NETISR_DISPATCH_H_
-#include "bluetooth.h"
-#include "ether.h"
-#include "ppp.h"
-#include "bridge.h"
-#include "pppoe.h"
-#include "pfsync.h"
-#endif
-
-/*
- * When adding functions to this list, be sure to add headers to provide
- * their prototypes in <net/netisr.h> (if necessary).
- */
-
-#ifdef INET
-#if NETHER > 0
- DONETISR(NETISR_ARP,arpintr);
-#endif
- DONETISR(NETISR_IP,ipintr);
-#endif
-#ifdef INET6
- DONETISR(NETISR_IPV6,ip6intr);
-#endif
-#ifdef MPLS
- DONETISR(NETISR_MPLS,mplsintr);
-#endif
-#ifdef NETATALK
- DONETISR(NETISR_ATALK,atintr);
-#endif
-#if NATM > 0
- DONETISR(NETISR_NATM,natmintr);
-#endif
-#if NPPP > 0
- DONETISR(NETISR_PPP,pppintr);
-#endif
-#if NBRIDGE > 0
- DONETISR(NETISR_BRIDGE,bridgeintr);
-#endif
-#if NPPPOE > 0
- DONETISR(NETISR_PPPOE,pppoeintr);
-#endif
-#if NBLUETOOTH > 0
- DONETISR(NETISR_BT,btintr);
-#endif
-#if NPFSYNC > 0
- DONETISR(NETISR_PFSYNC,pfsyncintr);
-#endif
- DONETISR(NETISR_TX,nettxintr);
