On 18/02/2019 18:45, Christian Spindeldreier wrote:
Hello Sebastian,
your changes work for us as well, now we are able to run a clean
version of the altcycv_devkit bsp on our DE10 board.
Thanks for testing.
Extending the BSP documentation helps a lot, but maybe you can add the
definition
Hello Sebastian,
your changes work for us as well, now we are able to run a clean version
of the altcycv_devkit bsp on our DE10 board.
Extending the BSP documentation helps a lot, but maybe you can add the
definition of the u-boot 'loadfdt' variable, does not seem to be defined
in any socfpg
Hello Christian,
I added some basic BSP documentation:
https://docs.rtems.org/branches/master/user/bsps/bsps-arm.html#altera-cyclone-v
On 14/02/2019 13:54, Christian Spindeldreier wrote:
we had to change the BSP_ARM_A9MPCORE_PERIPHCLK frequency to 100 MHz
as this is the frequency the L4 MP c
- Am 14. Feb 2019 um 23:38 schrieb Chris Johns chr...@rtems.org:
> On 14/2/19 5:57 am, Sebastian Huber wrote:
>> Unfortunately, I was not able to commit it.
>
> Did this get resolved?
I am travelling and will do this on Monday.
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On 14/2/19 5:57 am, Sebastian Huber wrote:
> Unfortunately, I was not able to commit it.
Did this get resolved?
Chris
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295-2767 | jan.som...@dlr.de
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> -Ursprüngliche Nachricht-
> Von: users [mailto:users-boun...@rtems.org] Im Auftrag von Christian
> Spindeldreier
> Gesendet: Donnerstag, 14. Februar 2019 13:55
> An: Sebastian Huber
> Cc: users
> Betreff: Re: device-tree example
Hello Sebastian,
we had to change the BSP_ARM_A9MPCORE_PERIPHCLK frequency to 100 MHz as
this is the frequency the L4 MP clock is set by Qsys or the SPL,
respectively. This meant adding a second board to the altera-cyclone-v
bsp differing only by this configuration option. Adapting the
config
Hello Christian,
I add the BSP section to the user manual today. Unfortunately, I was not able
to commit it. I tested also the latest RTEMS on the Cyclone V SoC Development
Kit and it worked fine. Does it now run on your board? The device tree is
normally provided by the U-Boot.
___
Hi Ian,
thank you for the insight into the rtems development with fdt.
As we did not manage to debug the boot process properly, my suspicion on
the device tree was incorrect. Actually our u-boot image generation and
boot commands were wrong. After searching through the rtems-kernel
repository
Hi Christian,
I am not familiar with the Cyclone, but we recently went through the
device tree learning curve moving to RTEMS5 and the creating a BPS for
the imx6ULL processor.
The thing with device tree is that what ever your BSP needs, is how you
have to name your device tree. Search your
Hi all,
we are trying to run rtems-5 on the Terasic DE10 Standard board
containing an Intel (former Altera) Cyclone V SoC-FPGA, which is
identical the the one on the one on the DK-DEV-5CSXC6N.
As there is the altcycv_devkit bsp within the rtems kernel we tried
simply to run a simple hello-wo
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