On 02/04/2019 11:08, Christian Spindeldreier wrote:
We use a nightly build of the RTEMS master, but we do not see the
RTEMS Fault Manager, as some kind of ISR prints out the content of the
register file and performs a warm reset when any error occurs. I
assume that u-boot (2018.11) and the MP
Hi,
thank you for the advice on the mmu config which we missed. One has to
enable the device memory region as follows:
arm_cp15_set_translation_table_entries(device_addr_start,
device_addr_end, ARMV7_MMU_DEVICE);
Afterwards one can access the device memory as described before.
We use a nig
Hello,
On 29/03/2019 12:57, Christian Spindeldreier wrote:
Hi,
currently we experimenting with the RTEMS-5 on a Cylcone V SoC-FPGA
using the altcycv_devkit BSP. Now we are trying to access a simple
hardware module connected to the HPS2FPGA Bridge via an AXI
interconnect. Our approach of simp
Hi,
currently we experimenting with the RTEMS-5 on a Cylcone V SoC-FPGA
using the altcycv_devkit BSP. Now we are trying to access a simple
hardware module connected to the HPS2FPGA Bridge via an AXI
interconnect. Our approach of simply write data to the corresponding
address or using the 'alt
