Re: Where to define CPU_SIMPLE_VECTORED_INTERRUPTS for RISC-V?

2020-06-02 Thread Sebastian Huber
On 02/06/2020 10:06, Schweikhardt, Jens (TSPCE3-TL4) wrote: we are using a customized RV32IMAF CPU with RTEMS and need to handle interrupts. I'm new to configuring low level things such as this and need a bit of guidance where goes what. I build using the RTEMS source builder. It appears that f

Where to define CPU_SIMPLE_VECTORED_INTERRUPTS for RISC-V?

2020-06-02 Thread Schweikhardt, Jens (TSPCE3-TL4)
Hello world, we are using a customized RV32IMAF CPU with RTEMS and need to handle interrupts. I'm new to configuring low level things such as this and need a bit of guidance where goes what. I build using the RTEMS source builder. It appears that for RISC-V a value for CPU_SIMPLE_VECTORED_INTERRU