Hello world, we are using a customized RV32IMAF CPU with RTEMS and need to handle interrupts. I'm new to configuring low level things such as this and need a bit of guidance where goes what. I build using the RTEMS source builder. It appears that for RISC-V a value for CPU_SIMPLE_VECTORED_INTERRUPTS is not defined, and thus treated as FALSE. Other CPUs, such as sparc, define it in cpukit/score/cpu/sparc/include/rtems/score/cpu.h.
Q: Should I simply add a macro definition to cpukit/score/cpu/riscv/include/rtems/score/cpu.h or is there a better (proper) way, say, passing it as an argument to sb-set-builder or sb-bootstrap or the configure script building the bsps? Jens ________________________________ Tesat-Spacecom GmbH & Co. KG Sitz: Backnang; Registergericht: Amtsgericht Stuttgart HRA 270977 Persoenlich haftender Gesellschafter: Tesat-Spacecom Geschaeftsfuehrungs GmbH; Sitz: Backnang; Registergericht: Amtsgericht Stuttgart HRB 271658; Geschaeftsfuehrung: Dr. Marc Steckling, Kerstin Basche, Ralf Zimmermann [banner] _______________________________________________ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
