On Tue, Jun 28, 2022 at 10:37:31PM +1000, Jonathan Gray wrote:
> On Sat, Jun 25, 2022 at 04:21:54AM -0700, Mike Larkin wrote:
> > On Fri, Jun 24, 2022 at 07:19:47PM +1000, Jonathan Gray wrote:
> > > +void
> > > +amd_cpu_cacheinfo(struct cpu_info *ci)
> > > +{
> > > + u_int eax, ebx, ecx, edx;
> > >
On Sat, Jun 25, 2022 at 04:21:54AM -0700, Mike Larkin wrote:
> On Fri, Jun 24, 2022 at 07:19:47PM +1000, Jonathan Gray wrote:
> > +void
> > +amd_cpu_cacheinfo(struct cpu_info *ci)
> > +{
> > + u_int eax, ebx, ecx, edx;
> > +
> > + /* used by vmm */
> > +
>
> If this is the only user of these f
On Fri, Jun 24, 2022 at 07:19:47PM +1000, Jonathan Gray wrote:
> Rewrite amd64 printing of cache details.
> Previously we looked at cpuid 0x8005 for L1/TLB details
> which Intel documents as reserved.
> And cpuid 0x8006 for L2 details.
>
> Intel also encode cache details in cpuid 4.
> AMD h
On 24.6.2022. 11:19, Jonathan Gray wrote:
> Rewrite amd64 printing of cache details.
> Previously we looked at cpuid 0x8005 for L1/TLB details
> which Intel documents as reserved.
> And cpuid 0x8006 for L2 details.
>
> Intel also encode cache details in cpuid 4.
> AMD have mostly the same
Rewrite amd64 printing of cache details.
Previously we looked at cpuid 0x8005 for L1/TLB details
which Intel documents as reserved.
And cpuid 0x8006 for L2 details.
Intel also encode cache details in cpuid 4.
AMD have mostly the same encoding with cpuid 0x801d
0x8005/0x8006 is
