On 24.6.2022. 11:19, Jonathan Gray wrote: > Rewrite amd64 printing of cache details. > Previously we looked at cpuid 0x80000005 for L1/TLB details > which Intel documents as reserved. > And cpuid 0x80000006 for L2 details. > > Intel also encode cache details in cpuid 4. > AMD have mostly the same encoding with cpuid 0x8000001d > 0x80000005/0x80000006 is used as a fallback in this diff > > The amount of cache visible to the thread is shown > and not which groups of cpus share a particular cache. > In the case of Alder Lake P, P cores have 1.25MB L2, each group of > 4 E cores shares a 2MB L2.
cpu0: AMD EPYC 7413 24-Core Processor, 2650.35 MHz, 19-01-01 before: cpu0: 32KB 64b/line 8-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line 8-way L2 cache cpu0: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu0: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative after: cpu0: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB 64b/line 8-way L2 cache, 32MB 64b/line 16-way L3 cache
