> -Original Message-
> From: Duan, Zhenzhong
> Sent: Wednesday, July 16, 2025 4:39 AM
> To: Nicolin Chen
> Cc: Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org; eric.au...@redhat.com;
> peter.mayd...@linaro.org; j...@nvidia.com; ddut...@redhat.com;
> berra...@
On Wed, Jul 16, 2025 at 09:15:54AM +0200, Cédric Le Goater wrote:
> Recent changes broke build on 32-bit host. Since there is no 32-bit
> support, restrict SEV to 64-bit.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/i386/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed
Refactor the creation of virtio devices. Use the accessors provided by
the Versal SoC to retrieve the reserved MMIO and IRQ space. Those are
defined in the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 +++
hw/arm/xlnx-versal-virt.c| 31
Refactor the DDR aperture regions creation using the VersalMap
structure. Device creation and FDT node creation are split into two
functions because the later must happen during ARM virtual bootloader
modify_dtb callback.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 7 +---
hw/a
Add the versal_get_num_cpu accessor to the Versal SoC to retrieve the
number of CPUs in the SoC. Use it in the xlnx-versal-virt machine.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 1 +
hw/arm/xlnx-versal-virt.c| 7 ---
hw/arm/xlnx-versal.c | 8
3 files
Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This
is in preparation for the versal2 version of the CRL.
Signed-off-by: Luc Michel
---
include/hw/misc/xlnx-versal-crl.h | 31 ++--
hw/misc/xlnx-versal-crl.c | 48 +++
2 file
Add a note in the DTB section explaining how to dump the generated DTB
using the dumpdtb machine option.
Signed-off-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/xlnx-versal-virt.rst
b/docs/syst
The CRL connects to various devices through link properties to be able
to reset them. The connections were dropped during the SoC refactoring.
Reintroduce them now.
Rely on the QOM tree to retrieve the devices to connect. The component
parts of the device names are chosen to match the properties o
Refactor the USB controller creation using the VersalMap structure.
Note that the connection to the CRL is removed for now and will be
re-added by next commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5 ---
hw/arm/xlnx-versal-virt.c| 56 +--
hw
The following commits will move FDT creation logic from the
xlnx-versal-virt machine to the xlnx-versal SoC itself. Prepare this by
passing the FDT handle to the SoC before it is realized. If no FDT is
passed, a dummy one is created internally as a stub to the fdt function
calls.
For now the SoC o
Refactor the GEM ethernet controllers creation using the VersalMap
structure.
Note that the connection to the CRL is removed for now and will be
re-added by next commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 -
hw/arm/xlnx-versal-virt.c| 54 -
hw/arm
Update the list of supported devices in the Versal SoCs.
Signed-off-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/xlnx-versal-virt.rst
b/docs/system/arm/xlnx-versal-virt.rst
index 2c63fbf519f..9
Split the xlnx-versal-virt machine type into a base abstract type and a
concrete type. There is no functional change. This is in preparation for
versal2 machine.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal-virt.c | 74 +++
1 file changed, 52 insertions(+)
Hi Zhenzhong,
On 7/8/25 1:05 PM, Zhenzhong Duan wrote:
> When vIOMMU is configured x-flts=on in scalable mode, stage-1 page table
> is passed to host to construct nested page table. We need to check
> compatibility of some critical IOMMU capabilities between vIOMMU and
> host IOMMU to ensure guest
On 7/15/25 6:21 PM, Paolo Abeni wrote:
> On 7/15/25 9:42 AM, Akihiko Odaki wrote:
>> On 2025/07/11 22:02, Paolo Abeni wrote:
>>> @@ -158,7 +159,10 @@ struct VirtIOPCIProxy {
>>> uint32_t nvectors;
>>> uint32_t dfselect;
>>> uint32_t gfselect;
>>> -uint32_t guest_features[2];
>
Refactor the UARTs creations. The VersalMap struct is now used to
describe the SoC and its peripherals. For now it contains the two UARTs
mapping information. The creation function now embeds the FDT creation
logic as well. The devices are now created dynamically using qdev_new
and (qdev|sysbus)_re
Refactor the XRAM devices creation using the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 6
hw/arm/xlnx-versal.c | 59 +---
2 files changed, 35 insertions(+), 30 deletions(-)
diff --git a/include/hw/arm/xlnx-ver
Refactor the TRNG device creation using the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 2 --
hw/arm/xlnx-versal.c | 18 ++
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/ar
Split the xlnx-versal device into two classes, a base, abstract class
and the existing concrete one. Introduce a VersalVersion type that will
be used across several device models when versal2 implementation is
added.
This is in preparation for versal2 implementation.
Signed-off-by: Luc Michel
--
The gem_init_register_masks function was called at init time but it
relies on the num-priority-queues property. Call it at realize time
instead.
Fixes: 4c70e32f05f ("net: cadence_gem: Define access permission for interrupt
registers")
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 2 +-
1
Refactor the CRL device creation using the VersalMap structure. The
connections to the RPU CPUs are temporarily removed and will be
reintroduced with next refactoring commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 ---
hw/arm/xlnx-versal.c | 36 +
Add the Versal Gen 2 (versal2) version of the Versal SoC family.
This version embeds up to 8 Cortex-A78AE cores (split into 4 clusters)
and 10 Cortex-R52 cores (split into 5 clusters). The similarities
between versal and versal2 in term of architecture allow to reuse the
VersalMap structure to almo
Refactor the BBRAM device creation using the VersalMap structure.
Note that the corresponding FDT node is removed. It does not correspond
to any real node in standard Versal DTBs. No matching drivers exist for
it.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 +--
hw/arm/xlnx-
Remove now unused macros in xlnx-versal.[ch]. Those macros have been
replaced by the VersalMap structure that serves as a central description
for the SoC. The ones still in use in the versal_unimp function are
inlined.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 204
Refactor the CFU device creation using the VersalMap structure. All
users of the APB IRQ OR gate have now been converted. The OR gate device
can be dropped.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 14 --
hw/arm/xlnx-versal.c | 258 ---
Improve the IRQ index in the VersalMap structure to turn it into a
descriptor:
- the lower 16 bits still represent the IRQ index
- bit 18 is used to indicate a shared IRQ connected to a OR gate
- bits 19 to 22 indicate the index on the OR gate.
This allows to share an IRQ among multiple d
Add the per_cluster_gic switch to the VersalCpuClusterMap structure.
When set, this indicates that a GIC instance should by created
per-cluster instead of globaly for the whole RPU or APU. This is in
preparation for versal2.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 15 +--
Add the versal2 version of the CRL device. For the implemented part, it
is similar to the versal version but drives reset line of more devices.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal-version.h | 1 +
include/hw/misc/xlnx-versal-crl.h| 329 ++
hw/misc/x
On 14.07.25 22:23, Vladimir Sementsov-Ogievskiy wrote:
On 14.07.25 13:41, Michael S. Tsirkin wrote:
On Thu, Jul 03, 2025 at 03:47:08PM +0300, Vladimir Sementsov-Ogievskiy wrote:
This field is mostly unused and sometimes confusing (we even have
a TODO-like comment to drop it). Let's finally do.
On Mon, Jul 14, 2025 at 01:03:06PM +0200, Paolo Bonzini wrote:
> From: Roy Hopkins
>
> The IGVM library allows Independent Guest Virtual Machine files to be
> parsed and processed. IGVM files are used to configure guest memory
> layout, initial processor state and other configuration pertaining t
On Wed, Jul 16, 2025 at 07:41:11PM +0800, Li Chen wrote:
> Hi Michael,
>
> Thanks for your kind review! All issues below have been fixed in v5:
> https://lore.kernel.org/qemu-devel/20250716111959.404917-5-me@linux.beauty/T/#m696cee9a95646add1b74b866c3d6761aa4c5c762
Past soft freeze now: I tagged
On 2025/07/15 23:52, Paolo Abeni wrote:
On 7/15/25 8:36 AM, Akihiko Odaki wrote:
On 2025/07/11 22:02, Paolo Abeni wrote:
The set_offload() argument list is already pretty long and
we are going to introduce soon a bunch of additional offloads.
Replace the offload arguments with a single struct
Hi Michael,
Thanks for your kind review! All issues below have been fixed in v5:
https://lore.kernel.org/qemu-devel/20250716111959.404917-5-me@linux.beauty/T/#m696cee9a95646add1b74b866c3d6761aa4c5c762
On Tue, 15 Jul 2025 02:45:31 +0800 Michael S. Tsirkin
wrote ---
> On Wed, May 28, 202
On Tue, Jul 15, 2025 at 07:57:57PM -0700, Nicolin Chen wrote:
> > +val = FIELD_EX32(s_accel->info.idr[5], IDR5, GRAN4K);
> > +if (val < FIELD_EX32(s->idr[5], IDR5, GRAN4K)) {
> > +s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, val);
> > +}
> > +val = FIELD_EX32(s_accel->inf
On 2025/07/16 0:40, Paolo Abeni wrote:
On 7/15/25 9:24 AM, Akihiko Odaki wrote:
On 2025/07/11 22:02, Paolo Abeni wrote:
+ */
+QEMU_BUILD_BUG_ON(VIRTIO_FEATURES_DWORDS != 2);
+if (virtio_128bit_features_needed(vdev)) {
There is no need to distinguish virtio_128bit_features_needed()
On 2025/07/16 18:14, Paolo Abeni wrote:
On 7/15/25 6:21 PM, Paolo Abeni wrote:
On 7/15/25 9:42 AM, Akihiko Odaki wrote:
On 2025/07/11 22:02, Paolo Abeni wrote:
@@ -158,7 +159,10 @@ struct VirtIOPCIProxy {
uint32_t nvectors;
uint32_t dfselect;
uint32_t gfselect;
-uint32
Hi Michael,
On Wed, 16 Jul 2025 19:42:42 +0800 Michael S. Tsirkin
wrote ---
> On Wed, Jul 16, 2025 at 07:41:11PM +0800, Li Chen wrote:
> > Hi Michael,
> >
> > Thanks for your kind review! All issues below have been fixed in v5:
> > https://lore.kernel.org/qemu-devel/20250716111959.
On 2025/07/16 0:43, Paolo Abeni wrote:
On 7/15/25 9:59 AM, Akihiko Odaki wrote:
On 2025/07/11 22:02, Paolo Abeni wrote:
@@ -785,11 +821,12 @@ VirtioStatus *qmp_x_query_virtio_status(const char *path,
Error **errp)
status->vhost_dev->nvqs = hdev->nvqs;
status->vhost_dev->v
Danny Canter writes:
> Joelle is correct, M3 and newer SoCs have support for the EL2 APIs.
Thanks for the confirmation. I'm looking at getting a M4 Mini for my
team so we can help review and test patches for HVF going forward.
Are you aware of any work that needs doing in the wider QEMU to supp
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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On 16/7/25 09:31, Sairaj Kodilkar wrote:
The ats_enabled field is set using HTTUNEN, which is wrong.
Fix this by removing the field as it is never used.
Fixes: d29a09ca68428 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 2
On 7/14/25 16:27, Steve Sistare wrote:
cpr-transfer may lose a VFIO interrupt because the KVM instance is
destroyed and recreated. If an interrupt arrives in the middle, it is
dropped. To fix, disable pended interrupts during cpr save, and pick
'pending' interrupts is more common.
up the pi
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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Hi Zhenzhong,
On 7/8/25 1:05 PM, Zhenzhong Duan wrote:
> PCI device supports two request types, Requests-without-PASID and
> Requests-with-PASID. Requests-without-PASID doesn't include a PASID TLP
> prefix, IOMMU fetches rid_pasid from context entry and use it as IOMMU's
> pasid to index pasid tab
+Peter, for info.
On 7/14/25 16:27, Steve Sistare wrote:
cpr-transfer may lose a VFIO interrupt because the KVM instance is
destroyed and recreated. If an interrupt arrives in the middle, it is
dropped. To fix, disable pended interrupts during cpr save, and pick
up the pieces. In more detail:
On 16/7/25 09:31, Sairaj Kodilkar wrote:
Define separate functions to trace MMIO write accesses instead of using
`trace_amdvi_mmio_read()` for both read and write.
Signed-off-by: Sairaj Kodilkar
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 23 ++-
1 file changed,
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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Dear QEMU developers,
QEMU has entered soft freeze for the 10.1 release cycle. You can find
the QEMU 10.1 release schedule here:
https://wiki.qemu.org/Planning/10.1
What is the soft feature freeze?
The soft feature freeze is the beginning of the stabilization phase of
QEMU's development process.
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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On 16/7/25 09:31, Sairaj Kodilkar wrote:
This series provides few cleanups and fixes for the amd iommu
The patches are based on top of 56c6e249b698 (v10.0.0-rc3) and Alejandro's
DMA remapping series [1].
56c6e249b698 is 4 months old, we are about to release v10.1.0-rc0.
What is the point of p
On 7/15/25 08:59, Zhenzhong Duan wrote:
Currently region_mr and mmap_mr size are recovered to original size when
base address is updated to non-PAGE_SIZE aligned, but still leave base_mr
with PAGE_SIZE size. This is harmless as base_mr is a only container but
still a bit confusing when executing
On 7/16/2025 6:07 PM, Philippe Mathieu-Daudé wrote:
On 16/7/25 09:31, Sairaj Kodilkar wrote:
This series provides few cleanups and fixes for the amd iommu
The patches are based on top of 56c6e249b698 (v10.0.0-rc3) and
Alejandro's
DMA remapping series [1].
56c6e249b698 is 4 months old, we
Hi Pierrick!
On 7/16/25 02:56, Pierrick Bouvier wrote:
On 7/15/25 8:13 PM, Gustavo Romero wrote:
Hi Pierrick,
On 7/14/25 22:26, Pierrick Bouvier wrote:
On 7/14/25 4:31 PM, Gustavo Romero wrote:
Hi folks,
Richard, thanks for v8. Pierrick, thanks for testing it. :)
On 7/14/25 14:09, Pierrick
tags/pull-9p-20250716
for you to fetch changes up to 44f51c1a3cf435daa82eb757740b59b1fd4fe71c:
hw/9pfs: move G_GNUC_PRINTF to header (2025-07-16 14:18:48 +0200)
9pfs changes:
* Tightens printf-style format checks. No behavi
From: Sean Wei
v9fs_string_sprintf() is annotated with G_GNUC_PRINTF(2, 3) in
9p-marshal.c, but the prototype in fsdev/9p-marshal.h is missing the
attribute, so callers that include only the header do not get format
checking.
Move the annotation to the header and delete the duplicate in the
sour
From: Sean Wei
v9fs_path_sprintf() is annotated with G_GNUC_PRINTF(2, 3) in
hw/9pfs/9p.c, but the prototype in hw/9pfs/9p.h is missing the
attribute, so callers that include only the header do not get format
checking.
Move the annotation to the header and delete the duplicate in the
source file.
Consider a system with 8 harts, where each hart supports 5
Guest Interrupt Files (GIFs), yielding 40 total GIFs.
If we launch a QEMU guest with over 5 vCPUs using
"-M virt,aia='aplic-imsic' -accel kvm,riscv-aia=hwaccel" – which
relies solely on VS-files (not SW-files) for higher performance – the
g
On Tue, 15 Jul 2025 10:01:21 -0700
Nicolin Chen wrote:
> On Tue, Jul 15, 2025 at 11:29:41AM +0100, Jonathan Cameron wrote:
> > > +if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,
> > > + IOMMU_VIOMMU_TYPE_ARM_SMMUV3,
> > > +
On 7/16/25 11:28, Daniel P. Berrangé wrote:
On Wed, Jul 16, 2025 at 09:15:54AM +0200, Cédric Le Goater wrote:
Recent changes broke build on 32-bit host. Since there is no 32-bit
support, restrict SEV to 64-bit.
Signed-off-by: Cédric Le Goater
---
hw/i386/Kconfig | 2 +-
1 file changed, 1 in
On Wed, Jul 16, 2025 at 05:23:57PM +0800, Yi Liu wrote:
> On 2025/7/16 12:05, Konstantin Belousov wrote:
> > On Wed, Jul 16, 2025 at 12:01:44PM +0800, Yi Liu wrote:
> > > On 2025/7/15 20:27, CLEMENT MATHIEU--DRIF wrote:
> > > >
> > > >
> > > > On 15/07/2025 10:27 am, David Woodhouse wrote:
> > >
On Wed, Jul 16, 2025 at 08:13:09AM +, Bernhard Beschow wrote:
>
>
> Am 15. Juli 2025 13:45:08 UTC schrieb "Daniel P. Berrangé"
> :
> >On Fri, Jul 11, 2025 at 12:00:24PM +0100, Daniel P. Berrangé wrote:
> >> On Fri, Jul 11, 2025 at 11:45:08AM +0100, Peter Maydell wrote:
> >> > On Tue, 17 Jun
On 2025/7/16 12:05, Konstantin Belousov wrote:
On Wed, Jul 16, 2025 at 12:01:44PM +0800, Yi Liu wrote:
On 2025/7/15 20:27, CLEMENT MATHIEU--DRIF wrote:
On 15/07/2025 10:27 am, David Woodhouse wrote:
On Tue, 2025-07-15 at 06:11 +, CLEMENT MATHIEU--DRIF wrote:
On 14/07/2025 11:22 pm, Ko
To align with current branding and ensure coherency with the upcoming
versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt.
Keep an alias of the old name to the new one for command-line backward
compatibility.
Signed-off-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst
Add support for the ARM Cortex-A78AE CPU.
Signed-off-by: Luc Michel
---
target/arm/tcg/cpu64.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 35cddbafa4c..337f8cf0c8d 100644
--- a/target/arm/tc
Add a way to configure the MP affinity value of the CPUs given their
core and cluster IDs. For the Versal APU CPUs, the MP affinity value is
directly given by the core ID.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 21 +
1 file changed, 21 insertions(+)
diff --git
From: Li Chen
This series introduces a new machine option, spcr=on|off, allowing users
to disable the ACPI SPCR (Serial Port Console Redirection) table.
By default, SPCR is enabled. Disabling it can help ensure that the guest's
console behavior is determined solely by kernel command-line paramete
From: Li Chen
The ACPI SPCR (Serial Port Console Redirection) table allows firmware
to specify a preferred serial console device to the operating system.
On ARM64 systems, Linux by default respects this table: even if the
kernel command line does not include a hardware serial console (e.g.,
"cons
From: Li Chen
Add ACPI SPCR table test case for RISC-V when SPCR was off.
Signed-off-by: Li Chen
Reviewed-by: Sunil V L
---
Notes:
Changes since v3: Add Reviewed-by from Sunil V L
tests/qtest/bios-tables-test.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a
From: Li Chen
Add ACPI SPCR table test case for ARM when SPCR was off.
Signed-off-by: Li Chen
---
tests/qtest/bios-tables-test.c | 20
1 file changed, 20 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 4dbc07ec5e..ede846f90
From: Li Chen
The virt machines always instantiate a PL011/16550 at UART0 and
describe it in ACPI (DSDT device node plus optional SPCR table). When
the command line contains “-serial none” there is no backend attached to
that UART, yet the guest still discovers it via ACPI and may try to use
it
On 03.06.2025 14:13, David Hildenbrand wrote:
When we unplug a vhost device, we end up calling vhost_dev_cleanup()
where we do a memory_listener_unregister().
This memory_listener_unregister() call will end up disconnecting the
listener from the address space through listener_del_address_space()
On Wed, Jul 16, 2025 at 06:26:37PM +0530, Sairaj Kodilkar wrote:
>
>
> On 7/16/2025 6:07 PM, Philippe Mathieu-Daudé wrote:
> > On 16/7/25 09:31, Sairaj Kodilkar wrote:
> > > This series provides few cleanups and fixes for the amd iommu
> > >
> > > The patches are based on top of 56c6e249b698 (v1
Prasad Pandit writes:
> On Tue, 15 Jul 2025 at 18:49, Fabiano Rosas wrote:
>> @@ -57,11 +57,9 @@ static const gchar *format_time_str(uint64_t us)
>> const char *units[] = {"us", "ms", "sec"};
>> int index = 0;
>>
>> -while (us > 1000) {
>> +while (us > 1000 && index + 1 < ARRAY
On 16.07.25 15:31, Michael Tokarev wrote:
On 03.06.2025 14:13, David Hildenbrand wrote:
When we unplug a vhost device, we end up calling vhost_dev_cleanup()
where we do a memory_listener_unregister().
This memory_listener_unregister() call will end up disconnecting the
listener from the address
Hi,
On 7/16/25 09:31, Sairaj Kodilkar wrote:
> Support the writes to the status register so that guest can reset the
> EventOverflow, EventLogInt, ComWaitIntr, etc bits after servicing the
> respective interrupt.
>
> Signed-off-by: Sairaj Kodilkar
> Reviewed-by: Vasant Hegde
> ---
> hw/i386/am
On Wed, Jul 16, 2025, 11:04 AM Markus Armbruster wrote:
> Okay to include this in my next QAPI PR?
>
That would be very convenient, thank you!
(And thanks to Akihiko Odaki for spotting and fixing the issue, even if it
took me a while to sort through our policy.)
>
On 7/16/25 09:31, Sairaj Kodilkar wrote:
> The AMD IOMMU is set up at boot time and uses PCI bus numbers + devfn
> for indexing into DTE. The problem is that before the guest started,
> all PCI bus numbers are 0 as no PCI discovery happened yet (BIOS or/and
> kernel will do that later) so relying o
On 11.07.2025 23:46, Mark Cave-Ayland wrote:
This series contains a few minor tidy-ups along with an implementation of the
logic to only allow ESP commands permitted in the current mode. The motivation
is to fix GitLab issue #2464 which causes Windows NT MIPS to bluescreen on
boot.
Patches 1 to
On 7/8/25 1:05 PM, Zhenzhong Duan wrote:
> This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the
> pasid entry and track PASID usage and future PASID tagged DMA address
> translation support in vIOMMU.
>
> VTDAddressSpace of PCI_NO_PASID is allocated when device is plugged an
John Snow writes:
> The way editable installs work has changed at some point since Fedora 40
> was released. Generally, we should be opting to use pyproject.toml
> installs (PEP517/518) - but those are not fully supported until v61 of
> setuptools, and CentOS Stream 9 ships v53.
>
> Until that ti
On 7/16/25 16:44, Paolo Abeni wrote:
Hi,
I'm observing boot failure for a rhel-9.7 VM. I'm using qemu git tree at
commit c079d3a31e.
No and I cannot reproduce it.
What host is it (processor) and kernel version?
Paolo
it core dumps with the following error:
qemu-system-x86_64: ../target/i3
On 7/16/25 5:22 PM, Paolo Bonzini wrote:
> On 7/16/25 16:44, Paolo Abeni wrote:
>> I'm observing boot failure for a rhel-9.7 VM. I'm using qemu git tree at
>> commit c079d3a31e.
>
> No and I cannot reproduce it.
>
> What host is it (processor) and kernel version?
Host CPU is AMD EPYC 7302 16-Cor
On 7/16/25 5:26 PM, Paolo Abeni wrote:
> On 7/16/25 5:22 PM, Paolo Bonzini wrote:
>> On 7/16/25 16:44, Paolo Abeni wrote:
>>> I'm observing boot failure for a rhel-9.7 VM. I'm using qemu git tree at
>>> commit c079d3a31e.
>>
>> No and I cannot reproduce it.
>>
>> What host is it (processor) and ker
On 14.07.2025 11:08, Zhao Liu wrote:
From: Chuang Xu
When QEMU is started with:
-cpu host,migratable=on,host-cache-info=on,l3-cache=off
-smp 180,sockets=2,dies=1,cores=45,threads=2
On Intel platform:
CPUID.01H.EBX[23:16] is defined as "max number of addressable IDs for
logical processors in th
Update the expected tables for the version change.
/*
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in
hex)
*/
[000h 004h] Signature : "FACP"[Fixed ACPI
Description Table (FADT)]
[004h 0004 004h]
Hi,
I'm observing boot failure for a rhel-9.7 VM. I'm using qemu git tree at
commit c079d3a31e.
My local conf is:
/configure --enable-kvm --enable-lto --target-list=x86_64-softmmu
enable-numa --enable-curses --enable-vhost-net
and the qemu command line:
/build/qemu-system-x86_64 -smp 4 -enab
Since RISC-V support is added only in ACPI 6.6, it should adhere to the
expected FADT and MADT versions. Update them.
Sunil V L (3):
bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes
hw/riscv/virt-acpi-build.c: Update FADT and MADT versions
tests/data/acpi/riscv64: Update e
Signed-off-by: Sunil V L
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..0c3f7a6cac 100644
--- a/tests/qtest/bios-tables-test-allowed-
RISC-V support is added only in ACPI 6.6. According to the ACPI 6.6
specification, the minor version of the Fixed ACPI Description Table
(FADT) should be 6, and the Multiple APIC Description Table (MADT)
should use revision 7. So, update the RISC-V FADT and MADT to reflect
correct versions.
Signed
On 7/16/25 09:31, Sairaj Kodilkar wrote:
> Current event logging code is broken, because of following issues
>
> 1. The code uses '|' instead of '&' to test the bit field, which causes
>vIOMMU to generate overflow interrupt for every log entry.
> 2. Code does not update the eventlog tail MMIO
On 15.07.2025 09:32, marcandre.lur...@redhat.com wrote:
From: Akihiko Odaki
vnc_worker_thread_loop() copies z_stream stored in its local VncState to
the persistent VncState, and the copied one is freed with deflateEnd()
later. However, deflateEnd() refuses to operate with a copied z_stream
and
Okay to include this in my next QAPI PR?
On Wed, Jul 16, 2025 at 5:26 PM Paolo Abeni wrote:
> On 7/16/25 5:22 PM, Paolo Bonzini wrote:
> > On 7/16/25 16:44, Paolo Abeni wrote:
> >> I'm observing boot failure for a rhel-9.7 VM. I'm using qemu git tree at
> >> commit c079d3a31e.
> >
> > No and I cannot reproduce it.
> >
> > What host is it
On Wed, Jul 16, 2025 at 06:07:31PM +0300, Michael Tokarev wrote:
> On 15.07.2025 09:32, marcandre.lur...@redhat.com wrote:
> > From: Akihiko Odaki
> >
> > vnc_worker_thread_loop() copies z_stream stored in its local VncState to
> > the persistent VncState, and the copied one is freed with deflate
On Wed, Jul 16, 2025 at 05:22:46PM +0200, Paolo Bonzini wrote:
> Date: Wed, 16 Jul 2025 17:22:46 +0200
> From: Paolo Bonzini
> Subject: Re: boot failure on top of current git
>
> On 7/16/25 16:44, Paolo Abeni wrote:
> > Hi,
> >
> > I'm observing boot failure for a rhel-9.7 VM. I'm using qemu git
On Wed, Jul 16, 2025 at 08:11:17AM +0200, Mauro Carvalho Chehab wrote:
> Em Tue, 15 Jul 2025 13:36:26 -0400
> "Michael S. Tsirkin" escreveu:
>
> > On Thu, Jun 12, 2025 at 05:17:24PM +0200, Mauro Carvalho Chehab wrote:
> > > Hi Michael,
> > >
> > > This is v10 of the patch series, rebased to appl
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