[PATCH 01/48] hw/net/cadence_gem: fix register mask initialization

[Luc Michel]

The gem_init_register_masks function was called at init time but it
relies on the num-priority-queues property. Call it at realize time
instead.

Fixes: 4c70e32f05f ("net: cadence_gem: Define access permission for interrupt 
registers")
Signed-off-by: Luc Michel <luc.mic...@amd.com>
---
 hw/net/cadence_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 50025d5a6f2..44446666deb 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1754,10 +1754,11 @@ static void gem_realize(DeviceState *dev, Error **errp)
 
     for (i = 0; i < s->num_priority_queues; ++i) {
         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
     }
 
+    gem_init_register_masks(s);
     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 
     s->nic = qemu_new_nic(&net_gem_info, &s->conf,
                           object_get_typename(OBJECT(dev)), dev->id,
                           &dev->mem_reentrancy_guard, s);
@@ -1774,11 +1775,10 @@ static void gem_init(Object *obj)
     CadenceGEMState *s = CADENCE_GEM(obj);
     DeviceState *dev = DEVICE(obj);
 
     DB_PRINT("\n");
 
-    gem_init_register_masks(s);
     memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
                           "enet", sizeof(s->regs));
 
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 }
-- 
2.50.0