Re: [PATCH v2] i386: Add missing cpu feature bits in EPYC-Rome model

; Richard Henderson > > ; Eduardo Habkost > > ; pankaj.gu...@cloud.ionos.com > > Subject: Re: [PATCH v2] i386: Add missing cpu feature bits in EPYC-Rome > > model > > > > On Wed, Mar 3, 2021 at 5:24 PM wrote: > > > > > > On Wednesday, 2021-03-03 at 09:4

RE: [PATCH v2] i386: Add missing cpu feature bits in EPYC-Rome model

> -Original Message- > From: Christian Ehrhardt > Sent: Thursday, April 1, 2021 3:06 AM > To: david.edmond...@oracle.com > Cc: Moger, Babu ; Paolo Bonzini > ; Richard Henderson > ; Eduardo Habkost > ; pankaj.gu...@cloud.ionos.com > Subject: Re: [PATCH v2] i3

Re: [PATCH v2] i386: Add missing cpu feature bits in EPYC-Rome model

On Wednesday, 2021-03-03 at 09:45:30 -06, Babu Moger wrote: > Found the following cpu feature bits missing from EPYC-Rome model. > ibrs: Indirect Branch Restricted Speculation > ssbd: Speculative Store Bypass Disable > > These new features will be added in EPYC-Rome-v2. The -cpu help outpu

[PATCH v2] i386: Add missing cpu feature bits in EPYC-Rome model

Found the following cpu feature bits missing from EPYC-Rome model. ibrs: Indirect Branch Restricted Speculation ssbd: Speculative Store Bypass Disable These new features will be added in EPYC-Rome-v2. The -cpu help output after the change. x86 EPYC-Rome (alias configured by ma