On Wednesday, 2021-03-03 at 09:45:30 -06, Babu Moger wrote: > Found the following cpu feature bits missing from EPYC-Rome model. > ibrs : Indirect Branch Restricted Speculation > ssbd : Speculative Store Bypass Disable > > These new features will be added in EPYC-Rome-v2. The -cpu help output > after the change. > > x86 EPYC-Rome (alias configured by machine type) > x86 EPYC-Rome-v1 AMD EPYC-Rome Processor > x86 EPYC-Rome-v2 AMD EPYC-Rome Processor > > Reported-by: Pankaj Gupta <[email protected]> > Signed-off-by: Babu Moger <[email protected]> > Signed-off-by: Pankaj Gupta <[email protected]>
Reviewed-by: David Edmondson <[email protected]> > --- > v2: Model-id remains same between EPYC-Rome-v1 and EPYC-Rome-v2. > Removed model-id in the patch. > > target/i386/cpu.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 6a53446e6a..30e7188b0e 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -4179,6 +4179,18 @@ static X86CPUDefinition builtin_x86_defs[] = { > .xlevel = 0x8000001E, > .model_id = "AMD EPYC-Rome Processor", > .cache_info = &epyc_rome_cache_info, > + .versions = (X86CPUVersionDefinition[]) { > + { .version = 1 }, > + { > + .version = 2, > + .props = (PropValue[]) { > + { "ibrs", "on" }, > + { "amd-ssbd", "on" }, > + { /* end of list */ } > + } > + }, > + { /* end of list */ } > + } > }, > { > .name = "EPYC-Milan", dme. -- And the sign said: long haired freaky people need not apply.
