Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions

2020-10-13 Thread Richard Henderson
On 10/12/20 8:37 AM, Peter Maydell wrote: > +nextlabel = gen_new_label(); > +tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[a->rn], 0, nextlabel); > +gen_jmp(s, read_pc(s) + a->imm); > + > +gen_set_label(nextlabel); > +tmp = load_reg(s, a->rn); > +store_reg(s, 14, tmp); > +gen_j

Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions

2020-10-13 Thread Peter Maydell
On Tue, 13 Oct 2020 at 18:30, Richard Henderson wrote: > Well, the only further comment is that, in the followup, only WLS gains the IT > block check. While I understand that's required to avoid an abort in QEMU for > this case, all three of the insns have that case as CONSTRAINED UNPREDICTABLE.

Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions

2020-10-13 Thread Richard Henderson
On 10/13/20 10:12 AM, Peter Maydell wrote: > On Tue, 13 Oct 2020 at 18:10, Richard Henderson > wrote: >> >> On 10/12/20 12:56 PM, Peter Maydell wrote: >>> On Mon, 12 Oct 2020 at 16:37, Peter Maydell >>> wrote: >>> This turns out not to work, because gen_jmp() always generates >>> a goto-tb for t

Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions

2020-10-13 Thread Peter Maydell
On Tue, 13 Oct 2020 at 18:10, Richard Henderson wrote: > > On 10/12/20 12:56 PM, Peter Maydell wrote: > > On Mon, 12 Oct 2020 at 16:37, Peter Maydell > > wrote: > > This turns out not to work, because gen_jmp() always generates > > a goto-tb for tb exit 0, and we hit the assert() that exit 0 > >

Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions

2020-10-13 Thread Richard Henderson
On 10/12/20 12:56 PM, Peter Maydell wrote: > On Mon, 12 Oct 2020 at 16:37, Peter Maydell wrote: >> >> v8.1M's "low-overhead-loop" extension has three instructions >> for looping: >> * DLS (start of a do-loop) >> * WLS (start of a while-loop) >> * LE (end of a loop) >> >> +static bool trans_WLS(

Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions

2020-10-12 Thread Peter Maydell
On Mon, 12 Oct 2020 at 16:37, Peter Maydell wrote: > > v8.1M's "low-overhead-loop" extension has three instructions > for looping: > * DLS (start of a do-loop) > * WLS (start of a while-loop) > * LE (end of a loop) > > +static bool trans_WLS(DisasContext *s, arg_WLS *a) > +{ > +/* M-profile

[PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions

2020-10-12 Thread Peter Maydell
v8.1M's "low-overhead-loop" extension has three instructions for looping: * DLS (start of a do-loop) * WLS (start of a while-loop) * LE (end of a loop) The loop-start instructions are both simple operations to start a loop whose iteration count (if any) is in LR. The loop-end instruction handl