> > -/* Descriptor 0x49 depends on CPU family/model, so it is not included
> > */
> > +/*
> > + * Descriptor 0x49 has 2 cases:
> > + * - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line
> > size.
> > + * - 3rd-level cache: 4MB, 16-way set associative, 64-byte l
On 6/20/2025 5:27 PM, Zhao Liu wrote:
> The legacy_l2_cache (2nd-level cache: 4 MByte, 16-way set associative,
> 64 byte line size) corresponds to descriptor 0x49, but at present
> cpuid2_cache_descriptors doesn't support descriptor 0x49 because it has
> multiple meanings.
>
> The 0x49 is necessa
The legacy_l2_cache (2nd-level cache: 4 MByte, 16-way set associative,
64 byte line size) corresponds to descriptor 0x49, but at present
cpuid2_cache_descriptors doesn't support descriptor 0x49 because it has
multiple meanings.
The 0x49 is necessary when CPUID 0x2 and 0x4 leaves have the consisten
