Re: [PATCH] target/riscv: Validate the mode in write_vstvec

On Mon, Jul 1, 2024 at 3:42 PM Jiayi Li wrote: > > Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. > Therefore, the encoding of the MODE should also be restricted to 0 and 1. > > Signed-off-by: Jiayi Li Thanks! Applied to riscv-to-apply.next Alistair > --- > target

Re: [PATCH] target/riscv: Validate the mode in write_vstvec

On 2024/7/1 10:25, Jiayi Li wrote: Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. Therefore, the encoding of the MODE should also be restricted to 0 and 1. Signed-off-by: Jiayi Li --- target/riscv/csr.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-)

Re: [PATCH] target/riscv: Validate the mode in write_vstvec

On Mon, Jul 1, 2024 at 3:42 PM Jiayi Li wrote: > > Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. > Therefore, the encoding of the MODE should also be restricted to 0 and 1. > > Signed-off-by: Jiayi Li Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cs

[PATCH] target/riscv: Validate the mode in write_vstvec

Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. Therefore, the encoding of the MODE should also be restricted to 0 and 1. Signed-off-by: Jiayi Li --- target/riscv/csr.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/targe