On 2024/7/1 10:25, Jiayi Li wrote:
Base on the riscv-privileged spec, vstvec substitutes for the usual stvec.
Therefore, the encoding of the MODE should also be restricted to 0 and 1.
Signed-off-by: Jiayi Li <[email protected]>
---
target/riscv/csr.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 432c59dc66..f9229d92ab 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3791,7 +3791,12 @@ static RISCVException read_vstvec(CPURISCVState *env,
int csrno,
static RISCVException write_vstvec(CPURISCVState *env, int csrno,
target_ulong val)
{
- env->vstvec = val;
+ /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+ if ((val & 3) < 2) {
+ env->vstvec = val;
+ } else {
+ qemu_log_mask(LOG_UNIMP, "CSR_VSTVEC: reserved mode not supported\n");
+ }
By the way, you can get the all the reviewers mail by checking the
patch with scripts/getmaintainer.pl.
Otherwise,
Reviewed-by: LIU Zhiwei <[email protected]>
Zhiwei
return RISCV_EXCP_NONE;
}
