On Wed, 16 Jul 2025 at 18:28, Philippe Mathieu-Daudé wrote:
>
> Have get_physical_address_range() return when HVF is not
> usable, allowing to try another accelerator if requested
> with '-accel hvf:tcg', reported here:
> https://gitlab.com/qemu-project/qemu/-/issues/2981
>
> Philippe Mathieu-Daud
On Wed, 16 Jul 2025 at 18:28, Philippe Mathieu-Daudé wrote:
>
> Emit a warning when HVF doesn't return the IPA bit length
> and return -1 as "this accelerator is not usable", allowing
> QEMU to try with the next one (when using '-accel hvf:tcg').
>
> Reported-by: Ivan Krasilnikov
> Resolves: https
On Wed, 16 Jul 2025 at 19:07, Steve Sistare wrote:
>
> Close a race condition that causes cpr-transfer to lose VFIO
> interrupts on ARM.
>
> CPR stops VCPUs but does not disable VFIO interrupts, which may continue
> to arrive throughout the transition to new QEMU.
>
> CPR calls kvm_irqchip_remove_
On Mon, 14 Jul 2025 at 17:01, Zenghui Yu wrote:
>
> * From v1 [1]:
> - add patch #1, as suggested by Peter
>
> [1] https://lore.kernel.org/r/20250315132030.95209-1-zenghui...@linux.dev
>
> Zenghui Yu (2):
> hvf: arm: Add permission check in GIC sysreg handle
On Mon, 14 Jul 2025 at 21:04, Philippe Mathieu-Daudé wrote:
>
> On 14/7/25 18:01, Zenghui Yu wrote:
> > Quoting Peter Maydell:
> >
> > " hvf_sysreg_read_cp() and hvf_sysreg_write_cp() do not check the .access
> >field of the ARMCPRegInfo to ensure t
lients_except(name, ncs,
> @@ -317,9 +316,6 @@ static void chr_closed_bh(void *opaque)
> qemu_chr_fe_set_handlers(&s->chr, NULL, NULL, net_vhost_user_event,
> NULL, opaque, NULL, true);
>
> -if (err) {
> -error_report_err(err);
> -}
> qapi_event_send_netdev_vhost_user_disconnected(name);
> }
>
Reviewed-by: Peter Maydell
thanks
-- PMM
eam_data_send(ioc, condition, data) == G_SOURCE_REMOVE) {
> NetPasstState *s = DO_UPCAST(NetPasstState, data, data);
> -Error *error;
> +Error *error = NULL;
>
> /* we need to restart passt */
> kill(s->pid, SIGTERM);
> --
> 2.49.0
>
>
Reviewed-by: Peter Maydell
thanks
-- PMM
> which can never be true in this error case. This makes the cleanup
> block dead code, as reported by Coverity (CID 1612371).
>
> Refactor the error handling to occur inline, removing the goto and
> the unreachable cleanup block.
>
Reviewed-by: Peter Maydell
thanks
-- PMM
error block
> to resolve the issue.
>
> Signed-off-by: Laurent Vivier
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
nd_net_clients_except(name, ncs,
> @@ -375,10 +374,6 @@ static void net_vhost_user_event(void *opaque,
> QEMUChrEvent event)
> /* Ignore */
> break;
> }
> -
> -if (err) {
> -error_report_err(err);
> -}
>
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 17 Jul 2025 at 18:44, Laurent Vivier wrote:
>
> If g_remove() fails, use warn_report() to log an error.
>
> Signed-off-by: Laurent Vivier
> ---
> net/passt.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
Reviewed-by: Peter Maydell
thanks
-- PMM
hard Henderson
> ---
> tcg/optimize.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 18 Jul 2025 at 18:46, Richard Henderson
wrote:
>
> There is no such thing as vector extract.
>
> Fixes: 932522a9ddc1 ("tcg/optimize: Fold and to extract during optimize")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3036
> Signed-off-by: Richard Henderson
> ---
> tcg/optimiz
FEAT_SVE_B16B16 adds bfloat16 versions of the FMLA and FMLS insns in
the "SVE floating-point multiply-accumulate writing addend" group,
encoded as sz=0b00.
Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Peter Maydell
---
target/arm/tcg/
different AH=1
behaviour) in a following commit.
Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 10 ++
target/arm/tcg/sve_helper.c| 5 +
target/arm/tcg/translate-sve.c | 22 +++
plete FEAT_SVE_B16B16.
thanks
-- PMM
Peter Maydell (10):
target/arm: Add BFADD, BFSUB, BFMUL (unpredicated)
target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated)
target/arm: Add BFMIN, BFMAX (predicated)
target/arm: Add BFMUL (indexed)
target/arm: Add BFMLA, BFMLS (vectors)
targe
FEAT_SVE_B16B16 adds bfloat16 versions of the FMLA and FMLS insns in
the SVE floating-point multiply-add (indexed) insn group. Implement
these.
Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Peter Maydell
---
target/arm/tcg/sve.decode | 2
we will access the wrong part of the
array.
The "s * 16" part of the expression is already aligned, so we only
need to use the H macro on the "e". Correct the macro usage.
Fixes: 1de7ecfc12d05 ("target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for
SVE2p1"
floatN_default_nan() to obtain this value.
Fixes: 1de7ecfc12d05 ("target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for
SVE2p1")
Signed-off-by: Peter Maydell
---
target/arm/tcg/sve_helper.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/
ME2p1 on -cpu max")
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper.h| 2 ++
target/arm/tcg/sve.decode | 1 +
target/arm/tcg/translate-sve.c | 2 +-
target/arm/tcg/vec_helper.c| 1 +
4 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/helper.h b/
: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 8
target/arm/tcg/sve_helper.c| 4
target/arm/tcg/translate-sve.c | 17 +++--
3 files changed, 27 insertions(+), 2 deletions(-)
to
set u=1 to match the assert.
Fixes: d2aa9a804ee6 ("target/arm: Implement LD1Q, ST1Q for SVE2p1")
Signed-off-by: Peter Maydell
---
target/arm/tcg/sve.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode
ADDQV, F{MIN, MAX}{NM}QV for
SVE2p1")
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-sve.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index fc76624b5a1..2ed440aff15 100644
--- a/targ
FEAT_SVE_B16B16 adds bfloat16 versions of the SVE floating point
(unpredicated) instructions, which are encoded via sz==0b00.
Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper.h| 3 +++
target/arm/tcg
s empty initialized before it is actually used.
>
> Fixes: f851cd65 ("ui/spice: Blit the scanout texture if its memory layout is
> not linear")
> Reported-by: Peter Maydell
> Cc: Marc-André Lureau
> Signed-off-by: Vivek Kasireddy
> ---
> ui/spice-displa
On Thu, 17 Jul 2025 at 18:05, Pierrick Bouvier
wrote:
> On 7/17/25 9:56 AM, Peter Maydell wrote:
> > I'm not really a fan of relying on the compiler to fold stuff
> > away -- it's fragile and there's no guarantee the compiler
> > will actually do it. In
On Tue, 15 Jul 2025 at 07:19, Cédric Le Goater wrote:
>
> commit ad8e0e8a0088 removed the "==" underlining the file title
> which broke documentation rendering. Add it back.
>
> Fixes: ad8e0e8a0088 ("docs: add support for gb200-bmc")
> Cc: Ed Tanous
>
On Mon, 14 Jul 2025 at 16:41, Pierrick Bouvier
wrote:
> As folding is not guaranteed by C standard, I'm not sure it's really
> possible to file a bug. However, since we rely on this behaviour in
> other parts, maybe it would be better to rewrite the condition on our side.
>
> By changing the code
On Wed, 16 Jul 2025 at 01:26, Jackson Donaldson wrote:
>
> Coverity Scan noted an unusual pattern in the
> MAX78000 aes device, with duplicated calls to
> set_decrypt. This commit adds a comment noting
> why the implementation is correct.
>
> Signed-off-by: Jackson Donaldson
> ---
> hw/misc/max7
On Mon, 14 Jul 2025 at 20:52, Philippe Mathieu-Daudé wrote:
>
> On 14/7/25 16:50, Peter Maydell wrote:
> > In commit b0438861efe ("host-utils: Avoid using __builtin_subcll on
> > buggy versions of Apple Clang") we added a workaround for a bug in
> > Apple C
On Thu, 17 Jul 2025 at 16:43, Daniel P. Berrangé wrote:
>
> On Thu, Jul 17, 2025 at 03:30:06PM +0200, Stefano Garzarella wrote:
> > On Wed, 16 Jul 2025 at 13:31, Daniel P. Berrangé
> > wrote:
> > > We really need to get something into 'make check' that runs the
> > > generator and compares its o
On Thu, 17 Jul 2025 at 16:16, Danny Canter wrote:
> - The new GIC APIs take care of interrupt injection, and would need to be
> used in concert with the EL2 APIs if you need interrupt support (highly
> likely 😬). This would
> be where I’d investigate on the QEMU end first to see if this would fi
On Thu, 17 Jul 2025 at 12:51, Philippe Mathieu-Daudé wrote:
>
> Hi Mark,
>
> On 15/7/25 08:19, Philippe Mathieu-Daudé wrote:
> > From: Mark Cave-Ayland
> >
> > In the cases where mixed DMA/non-DMA transfers are used or no data is
> > available, it is possible for the calculated transfer length to
On Fri, 30 May 2025 at 08:23, Paolo Bonzini wrote:
>
> From: Xiaoyao Li
>
> Invoke KVM_TDX_INIT_VM in kvm_arch_pre_create_vcpu() that
> KVM_TDX_INIT_VM configures global TD configurations, e.g. the canonical
> CPUID config, and must be executed prior to creating vCPUs.
>
> Use kvm_x86_arch_cpuid(
On Mon, 14 Jul 2025 at 12:13, Paolo Bonzini wrote:
>
> From: Xiaoyao Li
>
> Record the interrupt vector and the apic id of the vcpu that calls
> TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT.
>
> Inject the interrupt to TD guest to notify the completion of
> when notify interrupt vector is valid.
>
> Si
On Tue, 15 Jul 2025 at 05:42, Jason Wang wrote:
>
> From: Laurent Vivier
>
> This commit introduces support for passt as a new network backend.
> passt is an unprivileged, user-mode networking solution that provides
> connectivity for virtual machines by launching an external helper process.
>
>
On Tue, 15 Jul 2025 at 05:37, Jason Wang wrote:
>
> From: Laurent Vivier
>
> This commit adds support for the vhost-user interface to the passt
> network backend, enabling high-performance, accelerated networking for
> guests using passt.
>
> The passt backend can now operate in a vhost-user mode
On Tue, 15 Jul 2025 at 07:43, wrote:
>
> From: Vivek Kasireddy
>
> In cases where the scanout buffer is provided as a texture (e.g. Virgl)
> we need to check to see if it has a linear memory layout or not. If
> it doesn't have a linear layout, then blitting it onto the texture
> associated with t
On Tue, 15 Jul 2025 at 08:33, zhangzhijie wrote:
>
> 0. DW pcie support 64bit resource
> 1. DW version type using Linux kernel
>
> Signed-off-by: zhangzhijie
> ---
> hw/pci-host/designware.c | 12 +---
> include/hw/pci-host/designware.h | 2 +-
> 2 files changed, 10 insertions(+
On Tue, 15 Jul 2025 at 07:13, Cédric Le Goater wrote:
>
> On 7/11/25 14:01, Peter Maydell wrote:
> > On Fri, 4 Jul 2025 at 09:39, Cédric Le Goater wrote:
> >>
> >> From: Ed Tanous
> >>
> >> This patch updates the docs for support of gb200-bmc.
&
On Tue, 15 Jul 2025 at 01:00, Jackson Donaldson wrote:
>
> v5:
>
> > > +AES_KEY key;
> > > +if ((s->ctrl & TYPE) == 0) {
> > > +AES_set_encrypt_key(keydata, keylen, &key);
> > > +AES_set_decrypt_key(keydata, keylen, &s->internal_key);
> > > +AES_encrypt(s->data, s->
On Mon, 14 Jul 2025 at 18:44, Vacha Bhavsar
wrote:
> Regarding your question on whether the code handling the reading of the ZA
> storage would work on a big-endian host, I believe it would. I think this
> also applies to the pre-existing SVE code as well, based off of what I have
> read from t
; this commit preserves that behaviour
by using a local variable when doing the packet send.
Signed-off-by: Peter Maydell
---
Should the behaviour really be to truncate the packet at 64K
rather than flagging an error if the guest assembles descriptors
that combine to give a too-large packet?
---
hw
and the condition will
almost always be true, so we will reallocate the buffer more often
than we need to.
Correct the condition to test against tx_buffer_size, which is
where we track how big the allocated buffer is.
Signed-off-by: Peter Maydell
---
hw/net/npcm_gmac.c | 4 ++--
1 file changed,
uffer.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Peter Maydell
---
Disclaimer: this bugfix is based on reading the source code; I
don't have a test setup to confirm or test it.
---
hw/net/npcm_gmac.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm
ere we set buf = tx_send_buffer
but never used that value because we always updated buf to
something else later before using it.
Coverity: CID 1534027
Signed-off-by: Peter Maydell
---
hw/net/npcm_gmac.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/net/npcm_g
allocated
buffer.
The fourth patch fixes the Coverity error by dropping the
not-very-useful 'buf' local variable entirely.
thanks
-- PMM
Peter Maydell (4):
hw/net/npcm_gmac.c: Send the right data for second packet in a row
hw/net/npcm_gmac.c: Unify length and prev_buf_size variables
still
need to support Apple Clang 14.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3030
Signed-off-by: Peter Maydell
---
include/qemu/compiler.h | 13 -
include/qemu/host-utils.h | 2 +-
2 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/include/qemu/co
On Mon, 14 Jul 2025 at 15:29, Steve Sistare wrote:
>
> Close a race condition that causes cpr-transfer to lose VFIO
> interrupts on ARM.
>
> CPR stops VCPUs but does not disable VFIO interrupts, which may continue
> to arrive throughout the transition to new QEMU.
>
> CPR calls kvm_irqchip_remove_
in kvm_arm.h.
Fixes: f86d42205c2eba ("target/arm/meson: accelerator files are not needed in
user mode")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3033
Signed-off-by: Peter Maydell
---
I'm never sure when we prefer to use stub-functions in separate C files
vs when we prefer to ha
On Fri, 11 Jul 2025 at 15:20, Fabiano Rosas wrote:
>
> From: Peter Xu
>
> Add the latency distribution too for blocktime, using order-of-two buckets.
> It accounts for all the faults, from either vCPU or non-vCPU threads. With
> prior rework, it's very easy to achiev
On Fri, 4 Jul 2025 at 23:32, Jackson Donaldson wrote:
>
> This commit implements AES for the MAX78000
>
> Signed-off-by: Jackson Donaldson
> Reviewed-by: Peter Maydell
Hi; now this is upstream Coverity Scan noticed a possible
issue in this function (CID 1612247):
On Tue, 8 Jul 2025 at 23:14, Vacha Bhavsar
wrote:
>
> The QEMU GDB stub does not expose the ZA storage SME register to GDB via
> the remote serial protocol, which can be a useful functionality to debug SME
> code. To provide this functionality in Aarch64 target, this patch registers
> the
> SME r
On Sun, 13 Jul 2025 at 16:47, Zenghui Yu wrote:
>
> We don't synchronize vcpu registers from the hardware accelerator (e.g., by
> cpu_synchronize_state()) in the Dabort handler, so env->pc points to the
> instruction which has nothing to do with the Dabort at all.
>
> And it doesn't seem to make m
On Sat, 12 Jul 2025 at 17:04, 范艺豪 wrote:
>
> This will be used by the RT-Spark to create a machine.
> Subject: [PATCH v1] Add the stm32f407 SoC
>
> Signed-off-by: Yihao Fan
> ---
> MAINTAINERS| 7 ++
> hw/arm/Kconfig | 6 ++
> hw/arm/meson.build
On Mon, 14 Jul 2025 at 10:19, Stefano Garzarella wrote:
> On Thu, Jul 10, 2025 at 12:40:43PM -0400, Michael S. Tsirkin wrote:
> >> Q: should this file be listed in the "vhost" subcategory of
> >> MAINTAINERS?
> >> At the moment it only gets caught by "Network device backends".
>
> Maybe yes, but i
On Fri, 11 Jul 2025 at 18:04, Markus Armbruster wrote:
>
> Peter Maydell writes:
>
> > Coverity points out that the ivshmem-pci code has some error handling
> > cases where it incorrectly tries to use an invalid filedescriptor.
> > These generally happen becau
file descriptor was provided
when it was supposed to be. In particular:
* the error case in process_msg() only needs to close the fd
if one was provided
* process_msg_shmem() should fail if no fd was provided
Coverity: CID 1508726
Signed-off-by: Peter Maydell
---
Disclaimer: tested only with
he if() statement here, we correct the
indentation.)
Coverity: CID 1508111
Signed-off-by: Peter Maydell
---
linux-user/syscall.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index c600d5ccc0e..b7ec9a4f363 100644
--- a/linux
/NS")
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3016
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20250704165636.261888-1-peter.mayd...@linaro.org
---
target/arm/tcg/helper-a64.c | 20 +++-
1 file changed, 11 ins
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250707151547.196393-4-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/cpregs.h |3 +
target/arm/internals.h |2
From: Jackson Donaldson
This commit adds TRNG to max78000_soc
Signed-off-by: Jackson Donaldson
Message-id: 20250704223239.248781-10-jc...@duck.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/arm/max78000_soc.h | 2 ++
hw/arm/max78000_soc.c | 10
Signed-off-by: Jonathan Cameron
Tested-by: Li Zhijian
Message-id: 20250703104110.992379-6-jonathan.came...@huawei.com
Signed-off-by: Peter Maydell
---
tests/qtest/cxl-test.c | 58 -
tests/qtest/meson.build | 1 +
2 files changed, 46 insertions(+), 13
From: Cornelia Huck
Signed-off-by: Cornelia Huck
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Eric Auger
Message-id: 20250704141927.38963-5-coh...@redhat.com
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 3 +--
target/arm/cpu
From: Richard Henderson
This function isn't used.
Resolves: Coverity CID 1612139
Signed-off-by: Richard Henderson
Message-id: 20250710173945.115428-1-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper.h | 1 -
target/ar
From: Jackson Donaldson
This adds the target guide for the max78000FTHR
Signed-off-by: Jackson Donaldson
Message-id: 2025070626.624534-2-jc...@duck.com
[PMM: Moved doc to correct place in index; made underlines correct
length; added missing trailing newline; added SPDX]
Reviewed-by: Peter
From: Cornelia Huck
Signed-off-by: Cornelia Huck
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Eric Auger
Message-id: 20250704141927.38963-2-coh...@redhat.com
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 1 -
target/arm/cpu
From: Jonathan Cameron
Only add one very simple example as all the i386/pc examples will work
for arm/virt with a change to appropriate executable and appropriate
standard launch line for arm/virt. Note that max cpu is used to
ensure we have plenty of physical address space.
Suggested-by: Peter
...@duck.com
Signed-off-by: Peter Maydell
---
tests/functional/meson.build | 1 +
tests/functional/test_arm_max78000fthr.py | 48 +++
2 files changed, 49 insertions(+)
create mode 100755 tests/functional/test_arm_max78000fthr.py
diff --git a/tests/functional
From: Eric Auger
We may be miss some NV related GIC register save/restore. Until
we complete the study, let's add a migration blocker when the
maintenance IRQ is set.
Signed-off-by: Eric Auger
Message-id: 20250707164129.1167837-5-eric.au...@redhat.com
Suggested-by: Peter Maydell
Review
From: Cornelia Huck
Signed-off-by: Cornelia Huck
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Eric Auger
Message-id: 20250704141927.38963-3-coh...@redhat.com
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 2 --
target/arm/cpu
: Richard Henderson
Message-id: 20250707164129.1167837-6-eric.au...@redhat.com
[PMM: make "kernel doesn't have EL2 support" error message
distinct from the old "QEMU doesn't have KVM EL2 support" one]
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/virt
From: Jackson Donaldson
This commit implements the True Random Number
Generator for the MAX78000
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-9-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/misc/max78000_gcr.h | 1 +
include
27.38963-6-coh...@redhat.com
Signed-off-by: Peter Maydell
---
target/arm/kvm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 426f8b159e8..8ab0d692d36 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -230,7 +230,8 @@ stati
/max78000-user-guide.pdf
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-2-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/arm/max78000_soc.h | 35 +++
hw/arm/max78000_soc.c | 172 ++
hw/arm
d Henderson
Message-id: 20250707151547.196393-3-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/internals.h | 3 +
target/arm/helper.c| 514 +---
target/arm/t
ull pointer dereferences)
Suggested-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
system/qdev-monitor.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/system/qdev-monitor.c b/system/qdev-mo
IORT table.
Fixes:d6afe18b7242 ("hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables when
its=off")
Reviewed-by: Jonathan Cameron
Reviewed-by: Eric Auger
Reviewed-by: Donald Dutile
Tested-by: Eric Auger
Signed-off-by: Shameer Kolothum
Signed-off-by: Peter Maydell
---
hw/arm/virt-acpi-b
r_bridge instances pxb-cxl
docs/cxl: Add an arm/virt example.
qtest/cxl: Add aarch64 virt test for CXL
Peter Maydell (2):
target/arm: Don't enforce NSE,NS check for EL3->EL3 returns
hw/arm/virt: Allow virt extensions with KVM
Philippe Mathieu
-eric.au...@redhat.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/kvm.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 9fdf354f3bc..66723448554 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -251,6
-by: Eric Auger
Signed-off-by: Jonathan Cameron
Tested-by: Itaru Kitayama
Message-id: 20250703104110.992379-2-jonathan.came...@huawei.com
Signed-off-by: Peter Maydell
---
include/hw/cxl/cxl.h | 1 +
hw/cxl/cxl-host.c| 9 ++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git
From: Bernhard Beschow
Allows to run KVM guests inside the imx8mp-evk machine.
Fixes: a4eefc69b237 ("hw/arm: Add i.MX 8M Plus EVK board")
CC: qemu-stable
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Peter Maydell
---
hw/arm/fsl-imx8mp.c | 4 ++
ned-off-by: Cornelia Huck
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Eric Auger
Message-id: 20250704141927.38963-4-coh...@redhat.com
Signed-off-by: Peter Maydell
---
target/arm/tcg/cpu64.c | 14 +++---
1 file changed, 7 insertions(+), 7 deleti
From: Richard Henderson
Allow the call to be compiled out by protecting it
with tcg_enabled.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250707151547.196393-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.c| 4
-off-by: Haibo Xu
Signed-off-by: Miguel Luis
Signed-off-by: Eric Auger
Message-id: 20250707164129.1167837-2-eric.au...@redhat.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
include/hw/intc/arm_gicv3_common.h | 1 +
hw/arm/virt.c | 3 +++
hw/intc
From: Jackson Donaldson
This commit adds UART to max78000_soc
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-6-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/arm/max78000_soc.h | 3 +++
hw/arm/max78000_soc.c | 28
From: Jackson Donaldson
This commit adds AES to max78000_soc
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-12-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/arm/max78000_soc.h | 2 ++
hw/arm/max78000_soc.c | 12
to off.
Signed-off-by: Jonathan Cameron
Tested-by: Itaru Kitayama
Tested-by: Li Zhijian
Message-id: 20250703104110.992379-4-jonathan.came...@huawei.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
docs/system/arm/virt.rst | 9 +
include/hw/arm/virt.h| 4
hw
From: Haibo Xu
Introduce query support for KVM_CAP_ARM_EL2.
Signed-off-by: Haibo Xu
Signed-off-by: Miguel Luis
Signed-off-by: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250707164129.1167837-3-eric.au...@redhat.com
Signed-off-by: Peter
From: Jackson Donaldson
This commit implements UART support for the MAX78000
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-5-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/char/max78000_uart.h | 78 +
hw/char
From: Jackson Donaldson
This commit adds the instruction cache controller
to max78000_soc
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-4-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/arm/max78000_soc.h | 6 ++
hw/arm
From: Jackson Donaldson
This commit implements AES for the MAX78000
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-11-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/misc/max78000_aes.h | 68 ++
include/hw/misc
From: Jackson Donaldson
This commit implements the Global Control Register
for the MAX78000
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-7-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/misc/max78000_gcr.h | 129 +
hw
From: Jackson Donaldson
This commit implements the Instruction Cache Controller
for the MAX78000
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-3-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/misc/max78000_icc.h | 33 +
hw
From: Jackson Donaldson
This commit adds the Global Control Register to
max78000_soc
Signed-off-by: Jackson Donaldson
Reviewed-by: Peter Maydell
Message-id: 20250704223239.248781-8-jc...@duck.com
Signed-off-by: Peter Maydell
---
include/hw/arm/max78000_soc.h | 2 ++
hw/arm/max78000_soc.c
a hot enough path to justify an x86 only implementation.
Reviewed-by: Li Zhijian
Tested-by: Li Zhijian
Signed-off-by: Jonathan Cameron
Tested-by: Itaru Kitayama
Message-id: 20250703104110.992379-3-jonathan.came...@huawei.com
Signed-off-by: Peter Maydell
---
include/hw/cxl/cxl.h | 4 +-
inclu
On Fri, 11 Jul 2025 at 12:06, Jackson Donaldson wrote:
>
> This adds the target guide for the max78000FTHR
>
> Signed-off-by: Jackson Donaldson
> ---
Checkpatch wants an SPDX line for this new file -- can
you confirm that I can mark it as GPL-2.0-or-later like
the C files, please?
thanks
-- PMM
On Fri, 11 Jul 2025 at 11:45, Philippe Mathieu-Daudé wrote:
>
> On 10/7/25 16:33, Peter Maydell wrote:
> > This has reintroduced CID 1547782 (unreachable code).
> >
> > We can't get to this point, so why are we trying to call a
> > function here ? This is no
On Fri, 11 Jul 2025 at 12:06, Jackson Donaldson wrote:
>
> v2:
> Docs now build. Sorry about that
>
> v1:
> Adds .rST documentation and a functional test for the MAX78000FTHR machine
> as requested by Peter Maydell.
>
> Jackson Donaldson (2):
> docs/system: arm:
On Fri, 4 Jul 2025 at 09:39, Cédric Le Goater wrote:
>
> From: Ed Tanous
>
> This patch updates the docs for support of gb200-bmc.
>
> Signed-off-by: Ed Tanous
> Reviewed-by: Cédric Le Goater
> Link:
> https://lore.kernel.org/qemu-devel/20250703144249.3348879-3-etan...@nvidia.com
> Signed-off-
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