Hi,
On Sun, Jun 15, 2025 at 11:49 PM Cédric Le Goater wrote:
>
> Hi
>
> + Jeremy
>
> On 6/13/25 02:03, Joe Komlodi wrote:
> > Hi all,
> >
> > This series adds I3C bus support to QEMU and adds more functionality to the
> > Aspeed I3C controll
On Sun, Jun 15, 2025 at 11:42 PM Cédric Le Goater wrote:
>
> On 6/13/25 02:03, Joe Komlodi wrote:
> > Moves the Aspeed I3C model and traces into hw/i3c and creates I3C build
> > files.
> >
> > Signed-off-by: Joe Komlodi
>
>
> Reviewed-by: Cédric Le Goa
Adds behavior to the device reset register.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Stephen Longfield
---
hw/i3c/dw-i3c.c | 117
hw/i3c/trace-events | 1 +
2 files changed, 118 insertions(+)
diff --git a/hw/i3c
Moves the Aspeed I3C model and traces into hw/i3c and creates I3C build
files.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/Kconfig| 1 +
hw/arm/Kconfig| 1 +
hw/i3c/Kconfig
.
Signed-off-by: Joe Komlodi
Reviewed-by: Titus Rwantare
Reviewed-by: Patrick Venture
---
hw/i3c/Kconfig | 10 +
hw/i3c/meson.build | 1 +
hw/i3c/mock-i3c-target.c | 311 +++
hw/i3c/trace-events | 9 +
include/hw/i3c
The registers are only 32 bits wide, so we should cast the 64-bit value
passed in to only be 32 bits wide.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/i3c/dw-i3c.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/i3c
ve data to/from the controller,
the user reads/writes to a bidirectional TX/RX port.
Signed-off-by: Joe Komlodi
Reviewed-by: Stephen Longfield
Reviewed-by: Patrick Venture
---
hw/i3c/dw-i3c.c | 882 +++-
hw/i3c/trace-events | 10 +
incl
Allows us to attach the mock I3C target
Signed-off-by: Joe Komlodi
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 53d62cd08d..940418b46b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -532,6 +532,7 @@ config ASPEED_SOC
controller sets an interrupt to notify
software about what happened.
When the IBI is finished being serviced, the controller pushes the
result of the IBI and any data received from the target into the IBI
queue.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Stephen Longfield
To retrieve the I3C bus object normally, the order is Aspeed I3C -> DW
I3C[n] -> bus object, so make a nice wrapper for people to use.
Signed-off-by: Joe Komlodi
---
hw/i3c/aspeed_i3c.c | 9 +
include/hw/i3c/aspeed_i3c.h | 2 ++
2 files changed, 11 insertions(+)
diff --gi
Adds functionality to the CTRL register.
Signed-off-by: Joe Komlodi
Reviewed-by: Titus Rwantare
Reviewed-by: Patrick Venture
---
hw/i3c/dw-i3c.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index c5af331ac4
This adds support for hotplugging in I3C.
Conceptually this can be thought of as an I3C target being physically
socketed onto a board.
It is then the target's responsibility to go through the hot-join and
DAA process so it can participate on the bus.
Signed-off-by: Joe Komlodi
Review
Adds reset values for the new registers added.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/dw-i3c.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index b252903ea4..845fbd5efd 100644
--- a/hw
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/i3c/dw-i3c.c | 56 +
1 file changed, 56 insertions(+)
diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index ecd79aba8c..c58e12964c 100644
--- a/hw/i3c/dw-i3c.c
Adds read-only register masks for the DwC I3C controller.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/dw-i3c.c | 40
1 file changed, 40 insertions(+)
diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index 845fbd5efd..4f40f999f4
Adds the rest of the Designware register fields.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/dw-i3c.c | 216
1 file changed, 216 insertions(+)
diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index 4b1a3f3f07..b252903ea4
some way.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/i3c/core.c| 652 +++
hw/i3c/meson.build | 1 +
hw/i3c/trace-events | 16 ++
include/hw/i3c/i3c.h | 277 ++
4 files changed
Adds read-only register masks for the Aspeed I3C controller registers.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 16
1 file changed, 16 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 7a16dfec53..1ad25e5a00
RESET_CTRL and INTR_FORCE are write-only.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/dw-i3c.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index 4f40f999f4..bf51c00935 100644
--- a/hw/i3c/dw-i3c.c
+++ b/hw/i3c/dw-i3c.c
too
complicated, it just adds the device attempting to hotplug to the bus. It
is the device's responsibility to hot-join and go through the DAA process
to participate on the bus.
Thanks,
Joe
Joe Komlodi (19):
hw/misc/aspeed_i3c: Move to i3c directory
hw/i3c: Add bus support
hw/i3c: Sp
The Aspeed I3C IP block is technically an Aspeed IP block that manages
6 DW I3C controllers.
To help reflect this better and to make it easier for other SoCs to use
the DW I3C model, we'll split out the DW portion from the Aspeed
portion.
Signed-off-by: Joe Komlodi
---
hw/arm/Kc
Adds the rest of the Aspeed I3C controller register fields.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 54 +++--
1 file changed, 42 insertions(+), 12 deletions(-)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c
accel kvm
When built with --enable-ubsan.
Signed-off-by: Joe Komlodi
---
system/physmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/physmem.c b/system/physmem.c
index 16cf557d1a..ccd2b50da3 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -3204,6 +3204,7 @
https://freebsdgoogledeveloper.blogspot.com/2025/05/bhyve-and-powervm-solutions.html
In the source code of BHyve, there is a reference to qemu. The partial
solution is to ask the qemu poc and development what the CPU machine
parameters would equal the physical CPU. If that is not available, then the
virtualization would need to be the most recent CPU software translation.
I thought
region valid access size to allow for
64-bit accesses.
Signed-off-by: Joe Komlodi
---
hw/ssi/aspeed_smc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index faef1a8e5b..a1160187a4 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi
/github.com/gcc-mirror/gcc/blob/85b46d0795ac76bc192cb8f88b646a647acf98c1/libgcc/config/aarch64/sync-cache.c#L67)
which makes the first DSB unconditional, so we can fix the synchronization
issue by doing that as well.
Signed-off-by: Joe Komlodi
---
util/cacheflush.c | 4 +++-
1 file changed, 3 i
xecuted, which could lead to writes not being committed before execution.
This function is intended to be a copy of the upstream gcc one, which
does an unconditional DSB, so we can fix this by just doing that as well.
Thanks!
Joe
Joe Komlodi (1):
util/cacheflush: Make first DSB uncond
fd4b5 ("target/arm: Implement integer matrix multiply accumulate")
Signed-off-by: Joe Hattori
---
target/arm/tcg/vec_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 98604d170fd3..e9c3352023
On Thu, Feb 29, 2024 at 1:57 AM Peter Maydell wrote:
>
> On Thu, 29 Feb 2024 at 04:52, Joe Komlodi wrote:
> > On Wed, Feb 28, 2024 at 6:21 AM Peter Maydell
> > wrote:
> > > So as far as I can see, this patchset defines a bunch of mechanism,
> > > but no ac
On Wed, Feb 28, 2024 at 6:21 AM Peter Maydell wrote:
>
> On Tue, 27 Feb 2024 at 22:24, Joe Komlodi wrote:
> > This adds requester IDs to ARM CPUs and adds a "user-defined" memory
> > attribute.
> >
> > The requester ID on ARM CPUs is there because I'
ating TLBs. Similarly, we add the
requester ID during PTW, while populating the rest of the memory
attributes.
We add the requester ID during GPC and descriptor grabbing as well as
PTWs.
Signed-off-by: Joe Komlodi
---
target/arm/cpu.c | 4
target/arm/cpu.h | 6 ++
target/arm/ptw.
MEMTXATTRS_UNSPECIFIED, and we should respect
that instead of injecting user-defined attributes in the function.
Signed-off-by: Joe Komlodi
---
hw/pci/pci.c| 3 +++
include/hw/pci/pci_device.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 6496d027ca
ces that set attributes (using address_space_rw or some
other means), can add them on a per-device basis.
RFC because it's possible we might want this implementated in some other
way, and it touches some pretty frequently used code that I'm somewhat
familiar with, but not 100% fam
checkpatch.pl doesn't like these spaces around the colon, so we may as
well fix it up.
No functional change.
Signed-off-by: Joe Komlodi
---
include/exec/memattrs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
These are used to represent implementation-specific data.
These are based off of AMBA-AXI user signals, but can be used in any
implementation.
The length of 4-bits is arbitrary.
Signed-off-by: Joe Komlodi
---
include/exec/memattrs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include
During transactions, these get added to memory attributes at the same
time other attributes are added.
Similar to the requester ID, these are added on PTWs, GPCs, and
descriptor grabbing as well.
Signed-off-by: Joe Komlodi
---
target/arm/cpu.c | 2 ++
target/arm/cpu.h | 2 ++
target/arm/ptw.c
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
Reviewed-by: Peter Maydell
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
Reviewed-by: Peter Maydell
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/h
ward.
Basically as long as a reset happens in the middle of a transaction, the
state of the old transaction would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.
Thanks,
Joe
Joe Komlodi (3):
hw/
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
On Fri, Feb 16, 2024 at 5:04 PM Corey Minyard wrote:
>
> On Thu, Feb 08, 2024 at 04:39:10PM +, Peter Maydell wrote:
> > On Fri, 2 Feb 2024 at 20:48, Joe Komlodi wrote:
> > >
> > > It's possible for a reset to come in the middle of a transaction, which
&
On Thu, Feb 8, 2024 at 8:39 AM Peter Maydell wrote:
>
> On Fri, 2 Feb 2024 at 20:48, Joe Komlodi wrote:
> >
> > It's possible for a reset to come in the middle of a transaction, which
> > causes the bus to be in an old state when a new transaction comes in.
>
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_sl
n would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.
Thanks,
Joe
Joe Komlodi (3):
hw/i2c: core: Add reset
hw/i2c/smbus_slave: Add object path on error prints
hw/i2c: smbus_slave: Res
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c| 19 +++
include/hw/i2c/i2c.h | 2 +-
2 files changed, 20 insertions(+), 1 del
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 1300c9ec72..9f9afc25a4 1
Hi peter,
On Thu, Feb 1, 2024 at 7:24 AM Peter Maydell wrote:
>
> On Fri, 26 Jan 2024 at 00:56, Joe Komlodi wrote:
> >
> > It's possible for a reset to come in the middle of a transaction, which
> > causes the bus to be in an old state when a new transaction comes i
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c| 30 +-
include/hw/i2c/i2c.h | 6 +-
2 files changed, 30 inser
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_sl
of the old transaction would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.
Thanks,
Joe
Joe Komlodi (3):
hw/i2c: core: Add reset
hw/i2c/smbus_slave: Add object path on error prints
hw/i2c: s
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 1300c9ec72..e24a1ef472 1
On Thu, Jan 11, 2024 at 6:03 AM Corey Minyard wrote:
>
> On Wed, Jan 10, 2024 at 09:26:37PM +0000, Joe Komlodi wrote:
> > Hi all,
> >
> > This series adds some resets for SMBus and for the I2C core. Along with
> > it, we make SMBus slave error printing a little mor
+cminyard
Accidentally typed Corey's email address wrong in the initial send, oops.
On Wed, Jan 10, 2024 at 1:26 PM Joe Komlodi wrote:
>
> Hi all,
>
> This series adds some resets for SMBus and for the I2C core. Along with
> it, we make SMBus slave error printing a
for the SMBusDevice class, and
have the mux class invoke it when it resets.
Signed-off-by: Joe Komlodi
---
hw/i2c/i2c_mux_pca954x.c | 5 +
hw/i2c/smbus_slave.c | 3 +++
include/hw/i2c/smbus_slave.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_sl
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c| 30 +-
include/hw/i2c/i2c.h | 6 +-
2 files changed, 30 inser
straightforward.
Basically as long as a reset happens in the middle of a transaction, the
state of the old transaction would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.
Thanks,
Joe
Joe Komlodi (4
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 1300c9ec72..e24a1ef472 1
.
Since it's valid for CNTFRQ to have a non-zero reset value, we just
added an object property so people can set it.
Thanks!
Joe
Joe Komlodi (1):
hw/timer/sse-timer: Add CNTFRQ reset property
hw/timer/sse-timer.c | 4 +++-
include/hw/timer/sse-timer.h | 2 ++
2 files changed, 5 inser
e the CNTFRQ reset value.
Signed-off-by: Joe Komlodi
---
hw/timer/sse-timer.c | 4 +++-
include/hw/timer/sse-timer.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/timer/sse-timer.c b/hw/timer/sse-timer.c
index e92e83747d..a727f05bac 100644
--- a/hw/timer/sse-ti
Hi jeremy,
On Tue, Apr 11, 2023 at 2:17 AM Jeremy Kerr wrote:
>
> Hi Joe,
>
> > +static int aspeed_i3c_device_ibi_finish(I3CBus *bus)
> > +{
> > +AspeedI3CDevice *s = ASPEED_I3C_DEVICE(bus->qbus.parent);
> > +bool nack_and_disable_hj = A
QMP, so this adds properties to
allow people to do so.
Since the NPCM7xx is typically used to help manage other SoCs, hopefully
other people will find this useful as well.
Thanks!
Joe
Joe Komlodi (2):
hw/gpio/npcm7xx: Add GPIO DIN object property
hw/gpio/npcm7xx: Support qom-get on GPIO pin
;:"qom-set","arguments": {
"path":"/machine/soc/gpio[0]",
"property":"gpio-pins-in",
"value":1048576
}}
1048576 == 0x10, JSON does not support hex.
Signed-off-by: Joe Komlodi
---
hw/gpio/npcm7xx_gpio.c | 28
;:{
"path":"/machine/soc/gpio[0]",
"property":"gpio-pin-level"
}}
Signed-off-by: Joe Komlodi
---
hw/gpio/npcm7xx_gpio.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
index 2a7be60d8d..58db3a8d64
Hi Jeremy,
On Sun, Apr 2, 2023 at 11:14 PM Jeremy Kerr wrote:
>
> Hi Joe,
>
> > Adds a model to communicate to remote I3C devices over chardev. This
> > allows QEMU to communicate to I3C targets that exist outside of QEMU.
>
> Nice!
>
> I've been wanting s
ister space.
>
This is my understanding as well from an outside look.
>From a QEMU standpoint I could split off the dwc portion into a
dwc_i3c model, which the aspeed_i3c portion inherits from. I can do
that in a v2 if that sounds good with everyone.
Thanks,
Joe
> Cheers,
>
>
> Jeremy
Adds reset values for the new registers added.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index ae247e03bb..034a17ff8e 100644
--- a/hw/i3c
Adds read-only field masks for the I3C device and controller registers.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 56 +
1 file changed, 56 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
handle it in some way.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/i3c/core.c| 629 +++
hw/i3c/meson.build | 1 +
hw/i3c/trace-events | 16 ++
include/hw/i3c/i3c.h | 275 +++
4
.
Signed-off-by: Joe Komlodi
Reviewed-by: Titus Rwantare
Reviewed-by: Patrick Venture
---
hw/i3c/Kconfig | 10 ++
hw/i3c/meson.build | 1 +
hw/i3c/mock-target.c | 312 +++
hw/i3c/trace-events | 9 +
include/hw/i3c/mock
This adds support for hotplugging in I3C.
Conceptually this can be thought of as an I3C target being physically
socketed onto a board.
It is then the target's responsibility to go through the hot-join and
DAA process so it can participate on the bus.
Signed-off-by: Joe Komlodi
Review
Adds functionality to the CTRL register.
Signed-off-by: Joe Komlodi
Reviewed-by: Titus Rwantare
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 36
1 file changed, 36 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index
controller sets an interrupt to notify
software about what happened.
When the IBI is finished being serviced, the controller pushes the
result of the IBI and any data received from the target into the IBI
queue.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Stephen Longfield
Moves the Aspeed I3C model and traces into hw/i3c and create I3C build
files.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/Kconfig| 1 +
hw/arm/Kconfig| 1 +
hw/i3c/Kconfig
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/i3c/aspeed_i3c.c | 57 +
1 file changed, 57 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 2ed09234ff..b9aa1367d8 100644
--- a/hw/i3c
ng support. The hotplugging doesn't do anything too
complicated, it just adds the device attempting to hotplug to the bus. It is
the device's responsibility to hot-join and go through the DAA process to
participate on the bus.
Thanks!
Joe
Joe Komlodi (16):
hw/misc/aspeed_i3c: Move to i3
ve data to/from the controller,
the user reads/writes to a bidirectional TX/RX port.
Signed-off-by: Joe Komlodi
Reviewed-by: Stephen Longfield
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 848
hw/i3c/trace-events | 10 +
incl
This adds a remote I3C qtest using the Aspeed I3C controller and an
AST2600 board.
The qtest uses a basic Aspeed I3C driver to test:
- data transmission from controller to target
- data reception from target to controller
- target sending an IBI (with data bytes) to controller
Signed-off-by: Joe
Adds the rest of the fields laid out in the AST26xx datasheet.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 260 ++--
1 file changed, 248 insertions(+), 12 deletions(-)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c
tiated by target)
- 1-byte opcode
- 1-byte IBI address
- 1-byte RnW boolean
- 4-byte length of IBI payload from target as a LE uint32 (can be 0)
- n-byte IBI payload
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Stephen Longfield
---
hw/i3c/Kconfig | 5
RESET_CTRL and INTR_FORCE are write-only.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 6f514bef5e..79715f462d 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c
Adds behavior to the device reset register.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Stephen Longfield
---
hw/i3c/aspeed_i3c.c | 110 +---
hw/i3c/trace-events | 1 +
2 files changed, 104 insertions(+), 7 deletions(-)
diff
The registers are only 32 bits wide, so we should cast the 64-bit value
passed in to only be 32 bits wide.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/i3c/aspeed_i3c.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw
ocess of "$dnf makecache" after the
metadata has been downloaded?
Or am I missing something?
I am looking forward your expertise.
Joe
**
This email and attachments contain Ambarella Proprietary and/or Confidential
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_sl
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/hw/i2c/c
problems.
Thanks!
Joe
Joe Komlodi (2):
hw/i2c: smbus_slave: Reset state on reset
hw/i2c: core: Add reset
hw/i2c/core.c| 25 ++---
hw/i2c/smbus_slave.c | 9 +
2 files changed, 31 insertions(+), 3 deletions(-)
--
2.40.0.rc2.332.ga46443480c-goog
Will do, thanks
On Fri, May 27, 2022 at 1:42 PM Peter Maydell
wrote:
> On Fri, 27 May 2022 at 16:16, Joe Nosay wrote:
> >
> > Does the newest qemu source at github include the e2k cpu?
> > And, what is the exact address?
>
> Please keep emails on the mailing
The errors occur at the end of the attached file.
changing dir to build for make ""...
make[1]: Entering directory '/home/sossego/elbrus/qemu-e2k/build'
/usr/bin/ninja build.ninja && touch build.ninja.stamp
ninja: no work to do.
/usr/bin/python3 -B /home/sossego/elbrus/qemu-e2k/meson/meson.py intr
macros on registers.
Signed-off-by: Joe Komlodi
Change-Id: Ib94996b17c361b8490c042b43c99d8abc69332e3
---
hw/i2c/aspeed_i2c.c | 286 +---
include/hw/i2c/aspeed_i2c.h | 11 +-
2 files changed, 133 insertions(+), 164 deletions(-)
diff --git a/hw/i2c
extract FIELD1 via
SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE1, FIELD1)
or
SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE2, FIELD1)
Signed-off-by: Joe Komlodi
Change-Id: Id3dc53e7d2f8741c95697cbae69a81bb699fa3cb
---
include/hw/registerfields.h | 70 +
1 file c
The Aspeed I2C controller is used across other SKUs that have different
reserved bits for the ctrl_global_rsvd register.
Signed-off-by: Joe Komlodi
Change-Id: I606c5933c527274a9d2b0afe559b2e895767636c
---
hw/arm/aspeed_ast2600.c | 2 ++
hw/i2c/aspeed_i2c.c | 4
include/hw/i2c
grate over to the register API and then add new mode
support.
Thanks!
Joe
Joe Komlodi (7):
hw/registerfields: Add shared fields macros
aspeed: i2c: Add ctrl_global_rsvd property
aspeed: i2c: Migrate to registerfields API
aspeed: i2c: Use reg array instead of individual vars
aspeed: i2c: Ad
This cleans up some of the field accessing, setting, and clearing
bitwise operations, and wraps them in macros instead.
Signed-off-by: Joe Komlodi
Change-Id: I33018d6325fa04376e7c29dc4a49ab389a8e333a
---
hw/i2c/aspeed_i2c.c | 393 ++--
1 file changed, 196
Moves register definitions and short commonly used inlined functiosn to
the header file to help tidy up the implementation file.
Signed-off-by: Joe Komlodi
Change-Id: I34dff7485b6bbe3c9482715ccd94dbd65dc5f324
---
hw/i2c/aspeed_i2c.c | 266 ---
include/hw
Signed-off-by: Joe Komlodi
Change-Id: I566eb09f4b9016e24570572f367627f6594039f5
---
hw/i2c/aspeed_i2c.c | 3 +++
hw/i2c/trace-events | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 948d8dc2bb..f179f78ee9 100644
--- a/hw/i2c
new
mode, so we use SHARED_FIELD_XX macros to reuse most of the code between
the different modes.
For packet mode, most of the command behavior is the same compared to
other modes, but there are some minor changes to how interrupts are
handled compared to other modes.
Signed-off-by: Jo
controller doesn't care about it, and because any
errors would be the fault of the external software receiving the GPIO
transmitter packets.
Signed-off-by: Joe Komlodi
---
hw/gpio/Kconfig | 3 +
hw/gpio/google_gpio_transmitter.c | 127
For the GPIO transmitter to properly transmit on pin changes, it must
know the initial state of the GPIO pins on the controller.
Signed-off-by: Joe Komlodi
---
hw/gpio/npcm7xx_gpio.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
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