On 3/23/2024 3:14 AM, Atish Kumar Patra wrote:
> On Tue, Mar 12, 2024 at 6:53 AM Fei Wu wrote:
>>
>> The RISC-V Server Platform specification[1] defines a standardized set
>> of hardware and software capabilities, that portable system software,
>> such as OS and hypervisors can rely on being prese
On 3/8/2024 3:15 AM, Daniel Henrique Barboza wrote:
>
>
> On 3/7/24 04:36, Wu, Fei wrote:
>> On 3/6/2024 9:26 PM, Wu, Fei wrote:
>>> On 3/5/2024 1:58 PM, Wu, Fei wrote:
>>>> On 3/5/2024 3:43 AM, Daniel Henrique Barboza wrote:
>>>>>
>>
On 3/8/2024 6:15 AM, Marcin Juszkiewicz wrote:
> W dniu 4.03.2024 o 11:25, Fei Wu pisze:
>
>> The RISC-V Server Platform specification[1] defines a standardized
>> set of hardware and software capabilities, that portable system
>> software, such as OS and hypervisors can rely on being present in a
On 3/8/2024 5:20 PM, Andrew Jones wrote:
> On Thu, Mar 07, 2024 at 02:26:18PM +0800, Wu, Fei wrote:
>> On 3/7/2024 8:48 AM, Alistair Francis wrote:
>>> On Thu, Mar 7, 2024 at 5:13 AM Atish Kumar Patra
>>> wrote:
>>>>
>>>> On Wed, Mar 6, 2024 a
On 3/6/2024 9:26 PM, Wu, Fei wrote:
> On 3/5/2024 1:58 PM, Wu, Fei wrote:
>> On 3/5/2024 3:43 AM, Daniel Henrique Barboza wrote:
>>>
>>>
>>> On 3/4/24 07:25, Fei Wu wrote:
>>>> The harts requirements of RISC-V server platform [1] require RVA
On 3/7/2024 8:48 AM, Alistair Francis wrote:
> On Thu, Mar 7, 2024 at 5:13 AM Atish Kumar Patra wrote:
>>
>> On Wed, Mar 6, 2024 at 4:56 AM Wu, Fei wrote:
>>>
>>> On 3/6/2024 8:19 AM, Alistair Francis wrote:
>>>> On Mon, Mar 4, 2024 at 8:28 PM
On 3/5/2024 1:58 PM, Wu, Fei wrote:
> On 3/5/2024 3:43 AM, Daniel Henrique Barboza wrote:
>>
>>
>> On 3/4/24 07:25, Fei Wu wrote:
>>> The harts requirements of RISC-V server platform [1] require RVA23 ISA
>>> profile support, plus Sv48, Svadu, H, Sscofmpf
On 3/6/2024 8:19 AM, Alistair Francis wrote:
> On Mon, Mar 4, 2024 at 8:28 PM Fei Wu wrote:
>>
>> The RISC-V Server Platform specification[1] defines a standardized set
>> of hardware and software capabilities, that portable system software,
>> such as OS and hypervisors can rely on being present
Hi Conor,
On 3/6/2024 8:27 AM, Conor Dooley wrote:
> On Mon, Mar 04, 2024 at 06:25:39PM +0800, Fei Wu wrote:
>
>> +name = riscv_isa_string(cpu_ptr);
>> +qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
>> +g_free(name);
>
> Please use riscv_isa_write_fdt() h
On 3/5/2024 3:43 AM, Daniel Henrique Barboza wrote:
>
>
> On 3/4/24 07:25, Fei Wu wrote:
>> The harts requirements of RISC-V server platform [1] require RVA23 ISA
>> profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides
>> a virt CPU type (rvsp-ref) as compliant as possible.
>>
On 3/5/2024 3:35 AM, Daniel Henrique Barboza wrote:
>
>
> On 3/4/24 07:25, Fei Wu wrote:
>> The RISC-V Server Platform specification[1] defines a standardized set
>> of hardware and software capabilities, that portable system software,
>> such as OS and hypervisors can rely on being present in a
On 9/7/2023 11:46 PM, Anup Patel wrote:
> On Tue, Aug 1, 2023 at 4:16 AM Daniel Henrique Barboza
> wrote:
>>
>>
>>
>> On 7/30/23 22:53, Fei Wu wrote:
>>> riscv virt platform's memory started at 0x8000 and
>>> straddled the 4GiB boundary. Curiously enough, this choice
>>> of a memory layout wil
On 9/7/2023 5:10 PM, Eric Auger wrote:
> Hi,
>
> On 9/7/23 09:16, Philippe Mathieu-Daudé wrote:
>> Widening Cc to ARM/VFIO.
>>
>> On 4/8/23 11:15, Wu, Fei wrote:
>>> On 8/3/2023 11:07 PM, Andrew Jones wrote:
>>>> On Mon, Jul 31, 2023 at 09:53:17AM
On 8/3/2023 11:07 PM, Andrew Jones wrote:
> On Mon, Jul 31, 2023 at 09:53:17AM +0800, Fei Wu wrote:
>> riscv virt platform's memory started at 0x8000 and
>> straddled the 4GiB boundary. Curiously enough, this choice
>> of a memory layout will prevent from launching a VM with
>> a bit more than
On 8/1/2023 6:46 AM, Daniel Henrique Barboza wrote:
>
>
> On 7/30/23 22:53, Fei Wu wrote:
>> riscv virt platform's memory started at 0x8000 and
>> straddled the 4GiB boundary. Curiously enough, this choice
>> of a memory layout will prevent from launching a VM with
>> a bit more than 2000MiB
On 8/1/2023 6:46 AM, Daniel Henrique Barboza wrote:
>
>
> On 7/30/23 22:53, Fei Wu wrote:
>> riscv virt platform's memory started at 0x8000 and
>> straddled the 4GiB boundary. Curiously enough, this choice
>> of a memory layout will prevent from launching a VM with
>> a bit more than 2000MiB
On 6/28/2023 8:04 PM, Fei Wu wrote:
> v16
> --
> * rebase to latest commit 4329d049d (Jun 26)
> * original patch 1 (remove CONFIG_PROFILER) has already upstreamed so is
> removed from here
Hi Richard,
As CONFIG_PROFILER has been removed in upstream, could you please take a
look again at this re
On 6/13/2023 11:29 AM, Wu, Fei wrote:
> On 6/7/2023 8:24 PM, Fei Wu wrote:
>> v15
>> ---
>> This is a large change:
>> * remove all time related stuffs, including cmd 'info profile'
>> * remove the per-TB flag, use global flag instead
>> * remove
On 6/7/2023 8:24 PM, Fei Wu wrote:
> v15
> ---
> This is a large change:
> * remove all time related stuffs, including cmd 'info profile'
> * remove the per-TB flag, use global flag instead
> * remove tb_stats pause/filter, but add status
> * remove qemu_log changes, and use monitor_printf
> * use
On 6/7/2023 8:24 PM, Fei Wu wrote:
> v15
> ---
> This is a large change:
> * remove all time related stuffs, including cmd 'info profile'
> * remove the per-TB flag, use global flag instead
> * remove tb_stats pause/filter, but add status
> * remove qemu_log changes, and use monitor_printf
> * use
On 6/12/2023 3:17 PM, Richard Henderson wrote:
> On 6/12/23 03:44, Wu, Fei wrote:
>> On 6/7/2023 8:24 PM, Fei Wu wrote:
>>> +void hmp_info_tb(Monitor *mon, const QDict *qdict)
>>> +{
>>> + const int id = qdict_get_int(qdict, "id");
On 6/7/2023 8:24 PM, Fei Wu wrote:
> +void hmp_info_tb(Monitor *mon, const QDict *qdict)
> +{
> +const int id = qdict_get_int(qdict, "id");
> +g_autoptr(GString) buf = g_string_new("");
> +
> +if (!tcg_enabled()) {
> +monitor_printf(mon, "Only available with accel=tcg\n");
> +
On 6/9/2023 11:51 PM, Peter Maydell wrote:
> On Fri, 9 Jun 2023 at 15:32, Wu, Fei wrote:
>>
>> On 6/8/2023 5:23 PM, Peter Maydell wrote:
>>> On Thu, 8 Jun 2023 at 08:44, Wu, Fei wrote:
>>>> Is there any existing function to convert ram_addr_t to guest pa?
On 6/8/2023 5:23 PM, Peter Maydell wrote:
> On Thu, 8 Jun 2023 at 08:44, Wu, Fei wrote:
>>
>> On 6/7/2023 8:49 PM, Wu, Fei wrote:
>>> On 6/1/2023 10:40 AM, Richard Henderson wrote:
>>>> Did you really need something different than monitor_disas? You almost
On 6/7/2023 8:49 PM, Wu, Fei wrote:
> On 6/1/2023 10:40 AM, Richard Henderson wrote:
>>> +static int
>>> +__attribute__((format(printf, 2, 3)))
>>> +fprintf_log(FILE *a, const char *b, ...)
>>> +{
>>> + va_list ap;
>>> + va_start(ap, b
On 6/1/2023 10:40 AM, Richard Henderson wrote:
>> +static int
>> +__attribute__((format(printf, 2, 3)))
>> +fprintf_log(FILE *a, const char *b, ...)
>> +{
>> + va_list ap;
>> + va_start(ap, b);
>> +
>> + if (!to_string) {
>> + vfprintf(a, b, ap);
>> + } else {
>> + qemu_vl
On 6/1/2023 8:12 PM, Wu, Fei wrote:
> On 6/1/2023 10:40 AM, Richard Henderson wrote:
>> On 5/30/23 01:35, Fei Wu wrote:
>>> +static void do_dump_tbs_info(int total, int sort_by)
>>> +{
>>> + id = 1;
>>> + GList *i;
>>> + int
On 6/1/2023 10:03 PM, Richard Henderson wrote:
> On 5/31/23 22:44, Wu, Fei wrote:
>> On 6/1/2023 8:05 AM, Richard Henderson wrote:
>>> On 5/30/23 01:35, Fei Wu wrote:
>>>> From: "Vanderson M. do Rosario"
>>>>
>>>> If a TB has a
On 6/1/2023 7:51 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 5/30/2023 6:08 PM, Alex Bennée wrote:
>>>
>>> "Wu, Fei" writes:
>>>
>>>> On 5/30/2023 1:01 PM, Wu, Fei wrote:
>>>>&
On 6/1/2023 10:40 AM, Richard Henderson wrote:
> On 5/30/23 01:35, Fei Wu wrote:
>> +static void do_dump_tbs_info(int total, int sort_by)
>> +{
>> + id = 1;
>> + GList *i;
>> + int count = total;
>> +
>> + g_list_free(last_search);
>> + last_search = NULL;
>> +
>> + qht_iter(&tb_c
On 6/1/2023 9:30 AM, Richard Henderson wrote:
> On 5/30/23 01:35, Fei Wu wrote:
>> diff --git a/accel/tcg/tb-stats.c b/accel/tcg/tb-stats.c
>> index 805e1fc74d..139f049ffc 100644
>> --- a/accel/tcg/tb-stats.c
>> +++ b/accel/tcg/tb-stats.c
>> @@ -267,6 +267,25 @@ void do_hmp_tbstats_safe(CPUState *c
On 6/1/2023 9:23 AM, Richard Henderson wrote:
> On 5/30/23 01:35, Fei Wu wrote:
>> From: "Vanderson M. do Rosario"
>>
>> Adding tb_stats [start|pause|stop|filter] command to hmp.
>> This allows controlling the collection of statistics.
>> It is also possible to set the level of collection:
>> all,
On 6/1/2023 9:18 AM, Richard Henderson wrote:
> On 5/30/23 01:35, Fei Wu wrote:
>> From: "Vanderson M. do Rosario"
>>
>> -d tb_stats[[,level=(+all+jit+exec+time)][,dump_limit=]]
>>
>> "dump_limit" is used to limit the number of dumped TBStats in
>> linux-user mode.
>
> Why is user-mode special?
On 6/1/2023 9:08 AM, Richard Henderson wrote:
> On 5/30/23 01:35, Fei Wu wrote:
>> +static void collect_jit_profile_info(void *p, uint32_t hash, void
>> *userp)
>> +{
>> + struct jit_profile_info *jpi = userp;
>> + TBStatistics *tbs = p;
>> +
>> + jpi->translations += tbs->translations.tot
On 6/1/2023 8:05 AM, Richard Henderson wrote:
> On 5/30/23 01:35, Fei Wu wrote:
>> From: "Vanderson M. do Rosario"
>>
>> If a TB has a TBS (TBStatistics) with the TB_EXEC_STATS
>> enabled, then we instrument the start code of this TB
>> to atomically count the number of times it is executed.
>> We
On 6/1/2023 12:16 PM, Richard Henderson wrote:
> On 5/31/23 20:19, Wu, Fei wrote:
>> On 6/1/2023 8:01 AM, Richard Henderson wrote:
>>> On 5/30/23 01:35, Fei Wu wrote:
>>>> +/* TBStatistic collection controls */
>>>> +enum TBStatsStatus {
>>>>
On 6/1/2023 8:01 AM, Richard Henderson wrote:
> On 5/30/23 01:35, Fei Wu wrote:
>> +/* TBStatistic collection controls */
>> +enum TBStatsStatus {
>> + TB_STATS_DISABLED = 0,
>> + TB_STATS_RUNNING,
>> + TB_STATS_PAUSED,
>> + TB_STATS_STOPPED
>> +};
>
> I don't see what PAUSED or STOPPE
On 6/1/2023 7:59 AM, Richard Henderson wrote:
> On 5/30/23 01:35, Fei Wu wrote:
>> + /*
>> + * We want to fetch the stats structure before we start code
>> + * generation so we can count interesting things about this
>> + * generation.
>> + */
>> + if (tb_stats_collection_enab
On 5/30/2023 6:08 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 5/30/2023 1:01 PM, Wu, Fei wrote:
>>> On 5/30/2023 12:07 PM, Richard Henderson wrote:
>>>> On 5/29/23 04:49, Fei Wu wrote:
>>>>> +/*
>>>>> + * Th
On 5/30/2023 5:37 PM, Markus Armbruster wrote:
> Fei Wu writes:
>
>> This collects all the statistics for TBStatistics, not only for the
>> whole emulation but for each TB.
>>
>> Signed-off-by: Vanderson M. do Rosario
>> Signed-off-by: Alex Bennée
>> Signed-off-by: Fei Wu
>> ---
>> accel/tcg/
On 5/30/2023 6:08 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 5/30/2023 1:01 PM, Wu, Fei wrote:
>>> On 5/30/2023 12:07 PM, Richard Henderson wrote:
>>>> On 5/29/23 04:49, Fei Wu wrote:
>>>>> +/*
>>>>> + * Th
On 5/30/2023 1:01 PM, Wu, Fei wrote:
> On 5/30/2023 12:07 PM, Richard Henderson wrote:
>> On 5/29/23 04:49, Fei Wu wrote:
>>> +/*
>>> + * The TCGProfile structure holds data for analysing the quality of
>>> + * the code generation. The data is split between
On 5/30/2023 12:07 PM, Richard Henderson wrote:
> On 5/29/23 04:49, Fei Wu wrote:
>> +/*
>> + * The TCGProfile structure holds data for analysing the quality of
>> + * the code generation. The data is split between stuff that is valid
>> + * for the lifetime of a single translation and things that
On 5/25/2023 1:02 AM, Richard Henderson wrote:
> On 5/24/23 06:35, Wu, Fei wrote:
>> On 5/23/2023 8:45 AM, Richard Henderson wrote:
>>> On 5/18/23 06:57, Fei Wu wrote:
>>>> +void HELPER(inc_exec_freq)(void *ptr)
>>>> +{
>>&g
On 5/25/2023 1:02 AM, Richard Henderson wrote:
> On 5/24/23 06:35, Wu, Fei wrote:
>> On 5/23/2023 8:45 AM, Richard Henderson wrote:
>>> On 5/18/23 06:57, Fei Wu wrote:
>>>> +void HELPER(inc_exec_freq)(void *ptr)
>>>> +{
>>&g
On 5/23/2023 8:45 AM, Richard Henderson wrote:
> On 5/18/23 06:57, Fei Wu wrote:
>> +void HELPER(inc_exec_freq)(void *ptr)
>> +{
>> + TBStatistics *stats = (TBStatistics *) ptr;
>> + tcg_debug_assert(stats);
>> + ++stats->executions.normal;
>> +}
> ...
>> +static inline void gen_tb_exec_co
On 5/23/2023 8:45 AM, Richard Henderson wrote:
> On 5/18/23 06:57, Fei Wu wrote:
>> +void HELPER(inc_exec_freq)(void *ptr)
>> +{
>> + TBStatistics *stats = (TBStatistics *) ptr;
>> + tcg_debug_assert(stats);
>> + ++stats->executions.normal;
>> +}
> ...
>> +static inline void gen_tb_exec_co
On 5/23/2023 8:45 AM, Richard Henderson wrote:
> On 5/18/23 06:57, Fei Wu wrote:
>> +void HELPER(inc_exec_freq)(void *ptr)
>> +{
>> + TBStatistics *stats = (TBStatistics *) ptr;
>> + tcg_debug_assert(stats);
>> + ++stats->executions.normal;
>> +}
> ...
>> +static inline void gen_tb_exec_co
On 5/22/2023 6:25 PM, Thomas Huth wrote:
> On 18/05/2023 15.57, Fei Wu wrote:
>> Signed-off-by: Fei Wu
>> ---
>> docs/tb-stats.txt | 116 ++
>
> I'd suggest to add this file in the docs/devel folder instead, and maybe
> use a "tcg-" prefix for the file
On 4/22/2023 12:42 AM, Alex Bennée wrote:
>
> Fei Wu writes:
>
>> This patch series were done by Vanderson and Alex originally in 2019, I
>> (Fei Wu) rebased them on latest upstream from:
>> https://github.com/stsquad/qemu/tree/tcg/tbstats-and-perf-v10
>> and send out this review per Alex's
On 5/18/2023 9:57 PM, Fei Wu wrote:
> From: "Vanderson M. do Rosario"
>
> These commands allow the exploration of TBs generated by the TCG.
> Understand which one hotter, with more guest/host instructions... and
> examine their guest, host and IR code.
>
> The goal of this command is to allow th
On 5/18/2023 9:57 PM, Fei Wu wrote:
> From: "Vanderson M. do Rosario"
>
> To store statistics for each TB, we created a TBStatistics structure
> which is linked with the TBs. TBStatistics can stay alive after
> tb_flush and be relinked to a regenerated TB. So the statistics can
> be accumulated e
On 5/18/2023 9:57 PM, Fei Wu wrote:
> From: "Vanderson M. do Rosario"
>
> Adding tb_stats [start|pause|stop|filter] command to hmp.
> This allows controlling the collection of statistics.
> It is also possible to set the level of collection:
> all, jit, or exec.
>
> tb_stats filter allow to only
On 5/12/2023 4:42 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 4/22/2023 12:42 AM, Alex Bennée wrote:
>>>
>>> Fei Wu writes:
>>>
>>>> This patch series were done by Vanderson and Alex originally in 2019, I
>>>>
On 4/22/2023 12:42 AM, Alex Bennée wrote:
>
> Fei Wu writes:
>
>> This patch series were done by Vanderson and Alex originally in 2019, I
>> (Fei Wu) rebased them on latest upstream from:
>> https://github.com/stsquad/qemu/tree/tcg/tbstats-and-perf-v10
>> and send out this review per Alex's
On 5/3/2023 4:28 PM, Richard Henderson wrote:
> On 4/21/23 14:24, Fei Wu wrote:
>> From: "Vanderson M. do Rosario"
>>
>> If a TB has a TBS (TBStatistics) with the TB_EXEC_STATS
>> enabled, then we instrument the start code of this TB
>> to atomically count the number of times it is executed.
>> We
On 5/3/2023 4:12 PM, Richard Henderson wrote:
> On 4/21/23 14:24, Fei Wu wrote:
>> From: "Vanderson M. do Rosario"
>>
>> To store statistics for each TB, we created a TBStatistics structure
>> which is linked with the TBs. TBStatistics can stay alive after
>> tb_flush and be relinked to a regenera
On 4/21/2023 9:24 PM, Fei Wu wrote:
> From: "Vanderson M. do Rosario"
>
> These commands allow the exploration of TBs generated by the TCG.
> Understand which one hotter, with more guest/host instructions... and
> examine their guest, host and IR code.
>
> The goal of this command is to allow th
On 4/17/2023 9:01 PM, Wu, Fei wrote:
> On 4/17/2023 8:11 PM, Alex Bennée wrote:
>>
>> "Wu, Fei" writes:
>>
>>> On 4/11/2023 3:27 PM, Alex Bennée wrote:
>>>>
>>>> "Wu, Fei" writes:
>>>>
>>>>> On
On 4/17/2023 8:11 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 4/11/2023 3:27 PM, Alex Bennée wrote:
>>>
>>> "Wu, Fei" writes:
>>>
>>>> On 4/10/2023 6:36 PM, Alex Bennée wrote:
>>>>>
>>>
On 4/11/2023 3:27 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 4/10/2023 6:36 PM, Alex Bennée wrote:
>>>
>>> Richard Henderson writes:
>>>
>>>> On 4/6/23 00:46, Alex Bennée wrote:
>>>>> If your aim is to
On 4/12/2023 9:28 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 4/11/2023 3:27 PM, Alex Bennée wrote:
>>>
>>> "Wu, Fei" writes:
>>>
>>>> On 4/10/2023 6:36 PM, Alex Bennée wrote:
>>>>>
>>>
On 4/11/2023 3:27 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 4/10/2023 6:36 PM, Alex Bennée wrote:
>>>
>>> Richard Henderson writes:
>>>
>>>> On 4/6/23 00:46, Alex Bennée wrote:
>>>>> If your aim is to
On 4/11/2023 5:02 PM, Bin Meng wrote:
> When reading a non-existent CSR QEMU should raise illegal instruction
> exception, but currently it just exits due to the g_assert() check.
>
I verified that 'csrr t3, 0x4' in user space didn't cause qemu exit but
raised illegal instruction after applying th
On 4/10/2023 6:36 PM, Alex Bennée wrote:
>
> Richard Henderson writes:
>
>> On 4/6/23 00:46, Alex Bennée wrote:
>>> If your aim is to examine JIT efficiency what is wrong with the current
>>> "info jit" that you can access via the HMP? Also I'm wondering if its
>>> time to remove the #ifdefs fro
On 4/6/2023 3:46 PM, Alex Bennée wrote:
>
> Fei Wu writes:
>
>> The translation ratio of host to guest instruction count is one of the
>> key performance factor of binary translation. TCG doesn't collect host
>> instruction count at present, it does collect host instruction size
>> instead, alth
On 4/4/2023 3:11 PM, LIU Zhiwei wrote:
>
> On 2023/4/4 14:42, Wu, Fei wrote:
>> On 3/25/2023 6:54 PM, Richard Henderson wrote:
>>> This builds on Fei and Zhiwei's SUM and TB_FLAGS changes.
>>>
>>> * Reclaim 5 TB_FLAGS bits, since we nearly ran out
On 3/25/2023 6:54 PM, Richard Henderson wrote:
> This builds on Fei and Zhiwei's SUM and TB_FLAGS changes.
>
> * Reclaim 5 TB_FLAGS bits, since we nearly ran out.
>
> * Using cpu_mmu_index(env, true) is insufficient to implement
> HLVX properly. While that chooses the correct mmu_idx, it
Recent commit 0ee342256af92 switches to g_assert() for the predicate()
NULL check from returning RISCV_EXCP_ILLEGAL_INST. Qemu doesn't have
predicate() for un-allocated CSRs, then a buggy userspace application
reads CSR such as 0x4 causes qemu to exit, I don't think it's expected.
.global _start
On 3/28/2023 12:43 AM, Daniel Henrique Barboza wrote:
>
>
> On 3/25/23 07:54, Richard Henderson wrote:
>> This builds on Fei and Zhiwei's SUM and TB_FLAGS changes.
>>
>> * Reclaim 5 TB_FLAGS bits, since we nearly ran out.
>>
>> * Using cpu_mmu_index(env, true) is insufficient to implement
>
On 3/24/2023 9:02 AM, Wu, Fei wrote:
> On 3/23/2023 11:53 PM, Richard Henderson wrote:
>> On 3/22/23 19:44, Fei Wu wrote:
>>> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
>>> this assumption won't last as we are about to add more m
On 3/24/2023 10:37 AM, Richard Henderson wrote:
> On 3/23/23 18:20, Wu, Fei wrote:
>> I lack some background here, why should tb_flags be preferred if env has
>> the same info? Then for reading from tb_flags, we need to add it to
>> tb_flags first.
>
> We read from tb
On 3/24/2023 9:02 AM, Wu, Fei wrote:
> On 3/23/2023 11:53 PM, Richard Henderson wrote:
>> On 3/22/23 19:44, Fei Wu wrote:
>>> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
>>> this assumption won't last as we are about to add more m
On 3/24/2023 12:07 AM, Richard Henderson wrote:
> On 3/22/23 23:00, Wu, Fei wrote:
>>>> + ctx->priv = env->priv;
>>>
>>> This is not right. You should put env->priv into tb flags before you use
>>> it in translation.
>>>
>> I s
On 3/23/2023 11:53 PM, Richard Henderson wrote:
> On 3/22/23 19:44, Fei Wu wrote:
>> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
>> this assumption won't last as we are about to add more mmu_idx.
>>
>> Signed-off-by: Fei Wu
>> ---
>> target/riscv/cpu.h
On 3/23/2023 8:38 AM, Wu, Fei wrote:
> On 3/22/2023 9:19 PM, Richard Henderson wrote:
>> On 3/22/23 05:12, Fei Wu wrote:
>>> Kernel needs to access user mode memory e.g. during syscalls, the window
>>> is usually opened up for a very limited time through MSTATUS.SUM, t
On 3/23/2023 2:59 PM, LIU Zhiwei wrote:
>
> On 2023/3/23 14:00, Wu, Fei wrote:
>> On 3/23/2023 1:37 PM, LIU Zhiwei wrote:
>>> On 2023/3/23 10:44, Fei Wu wrote:
>>>> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
>>>> this
On 3/23/2023 2:00 PM, Wu, Fei wrote:
> On 3/23/2023 1:37 PM, LIU Zhiwei wrote:
>>
>> On 2023/3/23 10:44, Fei Wu wrote:
>>> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
>>> this assumption won't last as we are about to add mor
On 3/23/2023 1:37 PM, LIU Zhiwei wrote:
>
> On 2023/3/23 10:44, Fei Wu wrote:
>> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
>> this assumption won't last as we are about to add more mmu_idx.
> For patch set has more than 1 patch, usually add a cover letter.
This is co
On 3/23/2023 8:38 AM, Wu, Fei wrote:
> On 3/22/2023 9:19 PM, Richard Henderson wrote:
>> On 3/22/23 05:12, Fei Wu wrote:
>>> Kernel needs to access user mode memory e.g. during syscalls, the window
>>> is usually opened up for a very limited time through MSTATUS.SUM, t
On 3/22/2023 9:19 PM, Richard Henderson wrote:
> On 3/22/23 05:12, Fei Wu wrote:
>> Kernel needs to access user mode memory e.g. during syscalls, the window
>> is usually opened up for a very limited time through MSTATUS.SUM, the
>> overhead is too much if tlb_flush() gets called for every SUM chan
On 3/22/2023 8:37 PM, liweiwei wrote:
>
> On 2023/3/22 20:12, Fei Wu wrote:
>> Kernel needs to access user mode memory e.g. during syscalls, the window
>> is usually opened up for a very limited time through MSTATUS.SUM, the
>> overhead is too much if tlb_flush() gets called for every SUM change.
On 3/22/2023 11:36 AM, Wu, Fei wrote:
> On 3/22/2023 11:31 AM, Richard Henderson wrote:
>> On 3/21/23 19:47, Wu, Fei wrote:
>>>>> You should be making use of different softmmu indexes, similar to how
>>>>> ARM uses a separate index for PAN (privileged a
On 3/22/2023 11:31 AM, Richard Henderson wrote:
> On 3/21/23 19:47, Wu, Fei wrote:
>>>> You should be making use of different softmmu indexes, similar to how
>>>> ARM uses a separate index for PAN (privileged access never) mode. If
>>>> I read the manual pr
On 3/22/2023 9:58 AM, LIU Zhiwei wrote:
>
> On 2023/3/22 0:10, Richard Henderson wrote:
>> On 3/20/23 23:37, fei2...@intel.com wrote:
>>> From: Fei Wu
>>>
>>> Kernel needs to access user mode memory e.g. during syscalls, the window
>>> is usually opened up for a very limited time through MSTATUS.
On 3/21/2023 8:58 PM, liweiwei wrote:
>
> On 2023/3/21 14:37, fei2...@intel.com wrote:
>> From: Fei Wu
>>
>> Kernel needs to access user mode memory e.g. during syscalls, the window
>> is usually opened up for a very limited time through MSTATUS.SUM, the
>> overhead is too much if tlb_flush() get
On 3/21/2023 5:47 PM, liweiwei wrote:
>
> On 2023/3/21 17:14, Wu, Fei wrote:
>> On 3/21/2023 4:50 PM, liweiwei wrote:
>>> On 2023/3/21 16:40, Wu, Fei wrote:
>>>> On 3/21/2023 4:28 PM, liweiwei wrote:
>>>>> On 2023/3/21 14:37, fei2...@intel.com
On 3/21/2023 4:50 PM, liweiwei wrote:
>
> On 2023/3/21 16:40, Wu, Fei wrote:
>> On 3/21/2023 4:28 PM, liweiwei wrote:
>>> On 2023/3/21 14:37, fei2...@intel.com wrote:
>>>> From: Fei Wu
>>>>
>>>> Kernel needs to access user mode memory e.g
On 3/21/2023 4:28 PM, liweiwei wrote:
>
> On 2023/3/21 14:37, fei2...@intel.com wrote:
>> From: Fei Wu
>>
>> Kernel needs to access user mode memory e.g. during syscalls, the window
>> is usually opened up for a very limited time through MSTATUS.SUM, the
>> overhead is too much if tlb_flush() get
On 3/16/2023 10:07 AM, Wu, Fei wrote:
> On 3/15/2023 2:15 AM, Richard Henderson wrote:
>> On 3/14/23 06:47, Wu, Fei wrote:
>>> On 3/13/2023 11:00 PM, Richard Henderson wrote:
>>>> On 3/13/23 07:13, Wu, Fei2 wrote:
>>>>> Hi Richard,
>>>
On 3/15/2023 2:15 AM, Richard Henderson wrote:
> On 3/14/23 06:47, Wu, Fei wrote:
>> On 3/13/2023 11:00 PM, Richard Henderson wrote:
>>> On 3/13/23 07:13, Wu, Fei2 wrote:
>>>> Hi Richard,
>>>>
>>>> Sorry for disturbing you. I'm doing some
On 3/15/2023 10:40 PM, Wu, Fei wrote:
> Block chaining is one of the key performance factors of tcg. Currently
> tcg doesn't allow chaining across page boundary, an example can be found
> in gen_goto_tb() in target/riscv/translate.c.
>
> For user-mode tcg, it's poss
Block chaining is one of the key performance factors of tcg. Currently
tcg doesn't allow chaining across page boundary, an example can be found
in gen_goto_tb() in target/riscv/translate.c.
For user-mode tcg, it's possible to enable cross-page chaining with
careful attentions, assume there are cha
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