Re: [PATCH] target/riscv: rvv: Minimum VLEN needs to respect V/Zve extensions

Hi Daniel, Thanks for the question. Yes, you are right. And I find that I miss some patches for the part that you mentioned here. I'll update this patchset for it. Thanks, Max On Wed, Jul 2, 2025 at 10:48 PM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: > > >

Re: [PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions

Hi Nutty, Thanks for the suggestion. I'll provide a new version including the new description and a fix about another EEWs issue. Thanks, Max On Tue, Jul 1, 2025 at 2:43 PM Nutty Liu wrote: > On 6/27/2025 9:20 PM, Max Chou wrote: > > From: Anton Blanchard > > >

[PATCH v2 0/3] Fix some more RVV source overlap issues

This patchset is based on the v1 provided by Anoton Blanchard with following update: * Add the missing input EEWs checking rule for widen vector reduction instruction. Reference: * v1: 20250415043207.3512209-1-ant...@tenstorrent.com Anton Blanchard (3): target/riscv: rvv: Apply vext_check_in

[PATCH] target/riscv: rvv: Fix missing exit TB flow for ldff_trans

According to the V spec, the vector fault-only-first load instructions may change the VL CSR. So the ldff_trans TCG translation function should generate the lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to make sure the vl_eq_vlmax TB flag is correct. Signed-off-by: Max Chou

[PATCH] target/riscv: rvv: Minimum VLEN needs to respect V/Zve extensions

According to the RISC-V instruction set manual, the minimum VLEN needs to respect the following extensions: Extension Minimum VLEN * V 128 * Zve64[d|f|x] 64 * Zve32[f|x] 32 Signed-off-by: Max Chou --- target/riscv/tcg/tcg-cpu.c | 13 +++-- 1 file changed, 11

[PATCH v2 3/3] target/riscv: vadc and vsbc are vm=0 instructions

From: Anton Blanchard We were marking vadc and vsbc as vm=1 instructions, which meant vext_check_input_eew wouldn't detect mask vs source register overlaps. Signed-off-by: Anton Blanchard Reviewed-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn32.decode | 10 +- 1

[PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions

From: Anton Blanchard Handle the overlap of source registers with different EEWs. Signed-off-by: Anton Blanchard Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v2 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector integer/fp compare instructions

From: Anton Blanchard Handle the overlap of source registers with different EEWs. Signed-off-by: Anton Blanchard Reviewed-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff

Re: [PATCH 11/12] target/xtensa: replace FSF postal address with licenses URL

> > Signed-off-by: Sean Wei > --- > target/xtensa/core-dc232b/gdb-config.c.inc | 5 ++--- > target/xtensa/core-dc232b/xtensa-modules.c.inc | 5 ++--- > target/xtensa/core-fsf/xtensa-modules.c.inc| 5 ++--- > 3 files changed, 6 insertions(+), 9 deletions(-) Acked-by: Max Filippov -- Thanks. -- Max

Re: [PATCH v4 20/23] target/xtensa: call plugin trap callbacks

> > This change places hooks for xtensa targets. > > Signed-off-by: Julian Ganz > --- > target/xtensa/exc_helper.c | 6 ++ > 1 file changed, 6 insertions(+) Reviewed-by: Max Filippov -- Thanks. -- Max

[PATCH v3 00/10] Fix RVV encoding corner cases

estions and review. Anton Blanchard (2): target/riscv: rvv: Source vector registers cannot overlap mask register target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS Max Chou (8): target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to check mismatched i

[PATCH v3 01/10] target/riscv: rvv: Source vector registers cannot overlap mask register

From: Anton Blanchard Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans

[PATCH v3 06/10] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v3 05/10] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b

[PATCH v3 08/10] target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions

Handle the overlap of source registers with different EEWs. The vd of vector widening mul-add instructions is one of the input operands. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvbf16.c.inc | 9 ++- target

[PATCH v3 07/10] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v3 10/10] target/riscv: Fix the rvv reserved encoding of unmasked instructions

According to the v spec, the encodings of vcomoress.vm and vector mask-register logical instructions with vm=0 are reserved. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn32.decode | 18 +- 1 file changed, 9 insertions(+), 9 deletions

[PATCH v3 02/10] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

From: Anton Blanchard Signed-off-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v3 04/10] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v3 09/10] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv

[PATCH v3 03/10] target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to check mismatched input EEWs encoding constraint

According to the v spec, a vector register cannot be used to provide source operands with more than one EEW for a single instruction. The vs1 EEW of vrgatherei16.vv is 16. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans

Re: [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

On 2025/4/5 5:17 PM, Daniel Henrique Barboza wrote: On 3/29/25 11:44 AM, Max Chou wrote: Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou ---   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-   1

Re: [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions

On 2025/4/5 5:14 PM, Daniel Henrique Barboza wrote: On 3/29/25 11:44 AM, Max Chou wrote: Handle the overlap of source registers with different EEWs. The vs1 EEW of vrgatherei16.vv is 16. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Since you're marked as Author you don&#

Re: [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint

On 2025/4/5 5:09 PM, Daniel Henrique Barboza wrote: On 3/29/25 11:44 AM, Max Chou wrote: According to the v spec, a vector register cannot be used to provide source operands with more than one EEW for a single instruction. Signed-off-by: Max Chou ---   target/riscv/insn_trans

[PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint

According to the v spec, a vector register cannot be used to provide source operands with more than one EEW for a single instruction. Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 29 + 1 file changed, 29 insertions(+) diff --git a/target/riscv

[PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v2 01/12] target/riscv: rvv: Source vector registers cannot overlap mask register

From: Anton Blanchard Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++--- 1 file changed, 26

[PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v2 09/12] target/riscv: rvv: Apply vext_check_input_eew to vector widen instructions(OPMVV/OPMVX/etc.)

Handle the overlap of source registers with different EEWs. The vd of vector widening mul-add instructions is one of the input operands. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvbf16.c.inc | 9 ++- target/riscv

[PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions

Handle the overlap of source registers with different EEWs. The vs1 EEW of vrgatherei16.vv is 16. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv

[PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

[PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions

According to the v spec, the encodings of vcomoress.vm and vector mask-register logical instructions with vm=0 are reserved. Signed-off-by: Max Chou --- target/riscv/insn32.decode | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b

[PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v2 11/12] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v2 00/12] Fix RVV encoding corner cases

andling of register overlaps in vector widening/narrowing instructions 4. Fix unmasked RVV instruction encoding (e.g. vcompress.vm) Anton Blanchard (2): target/riscv: rvv: Source vector registers cannot overlap mask register target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS Ma

[PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

From: Anton Blanchard Signed-off-by: Anton Blanchard Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

Re: [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases

better to merge these fixes into this patchset to maintain the series’ cohesion and keep up to date. If you agree with this approach, I can integrate the fixes and submit a v2 of the patchset. Please let me know your thoughts, and we can discuss the details further. Thanks, Max On 2025/1/26 3:20

Re: [PATCH v2 03/11] target/xtensa: Finalize config in xtensa_register_core()

d. > > > > Signed-off-by: Philippe Mathieu-Daudé > > --- > > Cc: Max Filippov > > --- > > target/xtensa/cpu.h| 2 +- > > target/xtensa/helper.c | 5 +++-- > > 2 files changed, 4 insertions(+), 3 deletions(-) > > Reviewed-by: Richard Henderson Acked-by: Max Filippov -- Thanks. -- Max

Re: [PATCH 03/10] target/xtensa: Finalize config in xtensa_register_core()

On Mon, Feb 10, 2025 at 2:26 AM Philippe Mathieu-Daudé wrote: > > Only modify XtensaConfig within xtensa_register_core(), > when the class is registered, not when it is initialized. > > Signed-off-by: Philippe Mathieu-Daudé > --- > Cc: Max Filippov > --- >

Re: [PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

Reviewed-by: Max Chou On 2025/1/26 3:20 PM, Anton Blanchard wrote: Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

Re: [PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap

. Thanks, Max On 2025/1/26 3:20 PM, Anton Blanchard wrote: for 2*SEW = 2*SEW op SEW instructions vs2 and vs1 cannot overlap because it would mean a register is read with two different SEW settings. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed

Re: [PATCH 05/12] target/riscv: handle vslide1down.vx form mask and source overlap

the “vector slide instructions” to replace the specified vslide1down.vx instruction would be better.) The patch 06 also has the same issue. Thanks, Max On 2025/1/26 3:20 PM, Anton Blanchard wrote: Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file

Re: [PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap

.) Additionally, the patch 04/07/08/09/10 also have the same issue. Thanks, Max On 2025/1/26 3:20 PM, Anton Blanchard wrote: Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b

Re: [PATCH 02/12] target/riscv: handle vrgather mask and source overlap

Hi Anton, You might need to extend this patch or provide a new patch to handle the different EEWs source operands checking for the vrgatherei16.vv instruction (when SEW is not 16). Thanks, Max On 2025/1/26 3:20 PM, Anton Blanchard wrote: Signed-off-by: Anton Blanchard --- target/riscv

Re: [PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register

Reviewed-by: Max Chou On 2025/1/26 3:20 PM, Anton Blanchard wrote: Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 29

Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines

ally no board-level switch for the CPU endianness. Also big- and little-endian instruction encodings are different on otherwise identical xtensa CPUs. -- Thanks. -- Max

[PATCH] target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0

According to the Vector Reduction Operations section in the RISC-V "V" Vector Extension spec, "If vl=0, no operation is performed and the destination register is not updated." The vd should be updated when vl is larger than 0. Signed-off-by: Max Chou --- target/riscv

[PATCH] target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_set

In prop_vlen_set function, there is an incorrect comparison between vlen(bit) and vlenb(byte). This will cause unexpected error when user applies the `vlen=1024` cpu option with a vendor predefined cpu type that the default vlen is 1024(vlenb=128). Signed-off-by: Max Chou --- target/riscv/cpu.c

[PATCH] target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64

value to 64 bits during the TCG translation phase to ensure that the helper functions won't lost the higer 32 bits. Signed-off-by: Max Chou --- target/riscv/helper.h | 16 target/riscv/insn_trans/trans_rvv.c.inc | 50 - target/

Re: [RFC 1/1 v2] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

https://github.com/rnax/rvv_ldst_test max

Re: [PATCH v8 1/2] target/riscv: rvv: fix typo in vext continuous ldst function names

Reviewed-by: Max Chou max On 2024/12/18 10:23 PM, Craig Blackmore wrote: Replace `continus` with `continuous`. Signed-off-by: Craig Blackmore --- target/riscv/vector_helper.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/vector_helper.c b

Re: [PATCH v7 2/2] target/riscv: rvv: speed up small unit-stride loads and stores

On 2024/12/11 8:51 PM, Craig Blackmore wrote: Calling `vext_continuous_ldst_tlb` for load/stores smaller than 12 bytes significantly improves performance. Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Co-authored-by: Craig Blackmore Signed-off-by: Helene CHELIN Signed-off-by: P

Re: [PATCH 2/2] target/xtensa: Remove tswap() calls in semihosting simcall() helper

> +if (swap_needed) { > +bswap32s(&argptr); > +} > > cpu_memory_rw_debug(cs, > regs[3] + i * sizeof(uint32_t), -- Thanks. -- Max

Re: [PATCH 1/2] target/xtensa: Implement xtensa_isa_is_big_endian()

sa_isa_is_big_endian(xtensa_isa isa); This file doesn't include stdbool.h and other boolean functions in it (e.g. xtensa_opcode_is_branch()) return int. I'd suggest sticking with that. With that change: Acked-by: Max Filippov > #ifdef __cplusplus > } > diff --git a/target/xtensa

Re: [PATCH v6 1/1] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores

group multiple elements, the vstart value remains the index of the first element, which is not the actual element index that raised the exception. Max On 2024/12/4 8:29 PM, Craig Blackmore wrote: This patch improves the performance of the emulation of the RVV unit-stride loads and stores in the

Re: [RFC v5 1/1] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores

SR will get unexpected value. Because this flow does not update vstart CSR value. max

Re: [PATCH 13/21] target/xtensa: Factor out calls to set_use_first_nan()

et/xtensa/cpu.h| 6 ++ > target/xtensa/cpu.c| 2 +- > target/xtensa/fpu_helper.c | 33 +++-- > 3 files changed, 26 insertions(+), 15 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max

Re: [PATCH 14/21] target/xtensa: Explicitly set 2-NaN propagation rule

n flag because the propagation rules > will handle everything.) > > Signed-off-by: Peter Maydell > --- > target/xtensa/fpu_helper.c | 2 ++ > fpu/softfloat-specialize.c.inc | 12 +--- > 2 files changed, 3 insertions(+), 11 deletions(-) Reviewed-by: Max Filippov -- Thanks. -- Max

Re: [PATCH v6 0/7] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions

ping. On 2024/9/19 1:14 AM, Max Chou wrote: Hi, This version fixes several issues in v5 - The cross page bound checking issue - The mismatch vl comparison in the early exit checking of vext_ldst_us - The endian issue when host is big endian Thank for Richard Henderson's suggestions that

[PATCH v6 4/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store

agnostic, so remove the vstart early exit checking. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 129 +++ 1 file changed, 70 insertions(+), 59 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c2fcf8b3a00

[PATCH v6 2/7] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us

Because the real vl (evl) of vext_ldst_us may be different (e.g. vlm.v/vsm.v/etc.), so the VSTART_CHECK_EARLY_EXIT checking function should be replaced by checking evl in vext_ldst_us. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 5 - 1 file changed, 4 insertions(+), 1

[PATCH v6 6/7] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions

The vector unmasked unit-stride and whole register load/store instructions will load/store continuous memory. If the endian of both the host and guest architecture are the same, then we can group the element load/store to load/store more data at a time. Signed-off-by: Max Chou --- target/riscv

[PATCH v6 3/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

the element load/store through the original softmmu flow and the direct access host memory flow. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 363 +-- 1 file changed, 224 insertions(+), 139 deletions(-) diff --git a/target/riscv/vector_helper.c b/ta

[PATCH v6 5/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride load-only-first load instructions

The unmasked unit-stride fault-only-first load instructions are similar to the unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 98

[PATCH v6 7/7] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max Chou Reviewed-by: Ric

[PATCH v6 0/7] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions

v2: https://lore.kernel.org/all/20240531174504.281461-1-max.c...@sifive.com/ - v3: https://lore.kernel.org/all/20240613141906.1276105-1-max.c...@sifive.com/ - v4: https://lore.kernel.org/all/20240613175122.1299212-1-max.c...@sifive.com/ - v5: https://lore.kernel.org/all/20240717133936.713642-1-max.c...@sifive.

[PATCH v6 1/7] target/riscv: Set vdata.vm field for vector load/store whole register instructions

The vm field of the vector load/store whole register instruction's encoding is 1. The helper function of the vector load/store whole register instructions may need the vdata.vm field to do some optimizations. Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 1

Re: [PATCH] target/xtensa: Correct assert condition in handle_interrupt()

; Spotted because Coverity (correctly) thought the issue was still > outstanding. > --- > target/xtensa/exc_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Max Filippov -- Thanks. -- Max

Re: [RFC PATCH v5 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions

On 2024/7/25 2:04 PM, Richard Henderson wrote: On 7/17/24 23:39, Max Chou wrote: +static inline QEMU_ALWAYS_INLINE void +vext_continus_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host, +    void *vd, uint32_t evl, uint32_t reg_start, void *host

Re: [RFC PATCH v5 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

On 2024/7/25 1:51 PM, Richard Henderson wrote: On 7/17/24 23:39, Max Chou wrote: @@ -199,7 +212,7 @@ static void   vext_ldst_stride(void *vd, void *v0, target_ulong base,    target_ulong stride, CPURISCVState *env,    uint32_t desc, uint32_t vm

Re: [RFC PATCH v5 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

On 2024/7/25 2:05 PM, Richard Henderson wrote: On 7/17/24 23:39, Max Chou wrote: In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve

Re: [PATCH] target/xtensa: Make use of 'segment' in pptlb helper less confusing

per.c > @@ -991,7 +991,7 @@ uint32_t HELPER(rptlb1)(CPUXtensaState *env, uint32_t s) > uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v) > { > unsigned nhits; > -unsigned segment = XTENSA_MPU_PROBE_B; > +unsigned segment; The change suggests that coverity is ok

Re: [PATCH v3 12/12] target/riscv: Simplify probing in vext_ldff

Reviewed-by: Max Chou On 2024/7/19 9:07 AM, Richard Henderson wrote: The current pairing of tlb_vaddr_to_host with extra is either inefficient (user-only, with page_check_range) or incorrect (system, with probe_pages). For proper non-fault behaviour, use probe_access_flags with its nonfault

[RFC PATCH v5 1/5] target/riscv: Set vdata.vm field for vector load/store whole register instructions

The vm field of the vector load/store whole register instruction's encoding is 1. The helper function of the vector load/store whole register instructions may need the vdata.vm field to do some optimizations. Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 1

[RFC PATCH v5 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max Chou Reviewed-by: Ric

[RFC PATCH v5 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions

The vector unmasked unit-stride and whole register load/store instructions will load/store continuous memory. If the endian of both the host and guest architecture are the same, then we can group the element load/store to load/store more data at a time. Signed-off-by: Max Chou --- target/riscv

[RFC PATCH v5 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions

el.org/all/20240531174504.281461-1-max.c...@sifive.com/ - v3: https://lore.kernel.org/all/20240613141906.1276105-1-max.c...@sifive.com/ - v4: https://lore.kernel.org/all/20240613175122.1299212-1-max.c...@sifive.com/ Max Chou (5): target/riscv: Set vdata.vm field for vector load/store whol

[RFC PATCH v5 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store

agnostic, so remove the vstart early exit checking. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 123 +-- 1 file changed, 61 insertions(+), 62 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 23396a1b750

[RFC PATCH v5 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

the element load/store through the original softmmu flow and the direct access host memory flow. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 361 +-- 1 file changed, 220 insertions(+), 141 deletions(-) diff --git a/target/riscv/vector_helper.c b/ta

Re: [PATCH v2 13/13] target/riscv: Simplify probing in vext_ldff

On 2024/7/10 11:28 AM, Richard Henderson wrote: The current pairing of tlb_vaddr_to_host with extra is either inefficient (user-only, with page_check_range) or incorrect (system, with probe_pages). For proper non-fault behaviour, use probe_access_flags with its nonfault parameter set to true. S

Re: [RFC PATCH v4 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

On 2024/6/20 12:29 PM, Richard Henderson wrote: On 6/13/24 10:51, Max Chou wrote: This commit references the sve_ldN_r/sve_stN_r helper functions in ARM target to optimize the vector unmasked unit-stride load/store instructions by following items: * Get the loose bound of activate elements

Re: [RFC PATCH v4 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions

On 2024/6/20 12:38 PM, Richard Henderson wrote: On 6/13/24 10:51, Max Chou wrote: The vector unmasked unit-stride and whole register load/store instructions will load/store continuous memory. If the endian of both the host and guest architecture are the same, then we can group the element load

[RFC PATCH v4 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions

The vector unmasked unit-stride and whole register load/store instructions will load/store continuous memory. If the endian of both the host and guest architecture are the same, then we can group the element load/store to load/store more data at a time. Signed-off-by: Max Chou --- target/riscv

[RFC PATCH v4 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb

If there are not any QEMU plugin memory callback functions, checking before calling the qemu_plugin_vcpu_mem_cb function can reduce the function call overhead. Signed-off-by: Max Chou --- accel/tcg/ldst_common.c.inc | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a

[RFC PATCH v4 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

new interface to direct access host memory The original element load/store interface is replaced by the new element load/store functions with _tlb & _host postfix that means doing the element load/store through the original softmmu flow and the direct access host memory flow. Signed-off-by:

[RFC PATCH v4 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max Chou --- target/r

[RFC PATCH v4 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions

.1276105-1-max.c...@sifive.com/ Max Chou (5): accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store target/riscv: rvv: Provide a fast path using direct access t

[RFC PATCH v4 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store

The vector unit-stride whole register load/store instructions are similar to unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 185

[RFC PATCH v3 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions

The vector unmasked unit-stride and whole register load/store instructions will load/store continuous memory. If the endian of both the host and guest architecture are the same, then we can group the element load/store to load/store more data at a time. Signed-off-by: Max Chou --- target/riscv

[RFC PATCH v3 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb

If there are not any QEMU plugin memory callback functions, checking before calling the qemu_plugin_vcpu_mem_cb function can reduce the function call overhead. Signed-off-by: Max Chou --- accel/tcg/ldst_common.c.inc | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a

[RFC PATCH v3 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions

ore vector ld/st functions Previous version: - v1: https://lore.kernel.org/all/20240215192823.729209-1-max.c...@sifive.com/ - v2: https://lore.kernel.org/all/20240531174504.281461-1-max.c...@sifive.com/ Max Chou (5): accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb ta

[RFC PATCH v3 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store

The vector unit-stride whole register load/store instructions are similar to unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 185

[RFC PATCH v3 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

new interface to direct access host memory The original element load/store interface is replaced by the new element load/store functions with _tlb & _host postfix that means doing the element load/store through the original softmmu flow and the direct access host memory flow. Signed-off-by:

[RFC PATCH v3 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max Chou --- target/r

Re: [PATCH v3 2/5] target/xtensa: Restrict semihosting to TCG

ch is more correct (if we were to support a different accel). > > Reported-by: Anton Johansson > Signed-off-by: Philippe Mathieu-Daudé > --- > target/xtensa/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Max Filippov -- Thanks. -- Max

Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations

ions that suggested in tcg-op doc). I will provide next version with the helper function implementation like sve_ldN_r in ARM target. Thank you, Max On 2024/6/3 1:45 AM, Richard Henderson wrote: On 5/31/24 12:44, Max Chou wrote: The vector unit-stride load/store instructions (e.g. vle8.v/vs

[RFC PATCH v2 6/6] target/riscv: rvv: Optimize vl8re8.v/vs8r.v with limitations

endian Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 196 +++- 1 file changed, 194 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index bbac73bb12b..44763ccec06 100644 --- a

[RFC PATCH v2 1/6] target/riscv: Separate vector segment ld/st instructions

This commit separate the helper function implementations of vector segment load/store instructions from other vector load/store instructions. This can improve performance by avoiding unnecessary segment operation when NF = 1. Signed-off-by: Max Chou --- target/riscv/helper.h

[RFC PATCH v2 4/6] target/riscv: Add check_probe_[read|write] helper functions

The helper_check_probe_[read|write] functions wrap the probe_pages function to perform virtual address resolution for continuous vector load/store instructions. Signed-off-by: Max Chou --- target/riscv/helper.h| 4 target/riscv/vector_helper.c | 12 2 files changed

  1   2   3   4   5   6   7   8   9   10   >