Hi Nutty,
Thanks for the suggestion.
I'll provide a new version including the new description and a fix about
another EEWs issue.
Thanks,
Max
On Tue, Jul 1, 2025 at 2:43 PM Nutty Liu <liujin...@lanxincomputing.com>
wrote:
> On 6/27/2025 9:20 PM, Max Chou wrote:
> > From: Anton Blanchard <ant...@tenstorrent.com>
> >
> > Handle the overlap of source registers with different EEWs.
>
> Above description is the same as [patch v2 1/3].
> They are different functions.
> Maybe need to add some different description.
>
> Otherwise,
> Reviewed-by: Nutty Liu<liujin...@lanxincomputing.com>
>
> Thanks,
> Nutty
>
> >
> > Signed-off-by: Anton Blanchard <ant...@tenstorrent.com>
> > Signed-off-by: Max Chou <max.c...@sifive.com>
> > ---
> > target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> > index ec34d0d8c47..ac6f1d04c6d 100644
> > --- a/target/riscv/insn_trans/trans_rvv.c.inc
> > +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> > @@ -3293,6 +3293,7 @@ static bool reduction_check(DisasContext *s,
> arg_rmrr *a)
> > {
> > return require_rvv(s) &&
> > vext_check_isa_ill(s) &&
> > + vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew,
> a->vm) &&
> > vext_check_reduction(s, a->rs2);
> > }
> >
> > @@ -3309,7 +3310,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
> > static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
> > {
> > return reduction_check(s, a) && (s->sew < MO_64) &&
> > - ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
> > + ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
> > + vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1,
> a->vm);
> > }
> >
> > GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
>
