On Thu, Jul 17, 2025 at 7:52 AM Markus Armbruster wrote:
>
> The QAPI doc generator recently started to auto-generate return
> documentation when there is no "Returns:" section (commit 636c96cd77d
> "qapi: Fix undocumented return values by generating something").
> Remove "Returns:" sections where
On Wed, Jul 02, 2025 at 02:10:45PM +0200, Kevin Wolf wrote:
> Am 20.06.2025 um 02:08 hat Stefan Hajnoczi geschrieben:
> > When an AioHandler is enqueued on ctx->submit_list for removal, the
> > fill_sq_ring() function will submit an io_uring POLL_REMOVE operation to
> > cancel the in-flight POLL_AD
On Thu, Jul 17, 2025 at 4:44 AM Alex Bennée wrote:
>
> Manos Pitsidianakis writes:
>
> > Add argument parsing to functional tests to improve developer experience
> > when running individual tests. All logs are printed to stdout
> > interspersed with TAP output.
> >
> > ./pyvenv/bin/python3 ../t
On Thu, Jul 17, 2025 at 7:52 AM Markus Armbruster wrote:
>
> Tagged sections are only recognized at the beginning of a paragraph.
> guest-network-get-route's Returns: isn't, and therefore gets rendered
> as ordinary text within its paragraph:
>
> Retrieve information about route of network. Re
On Mon, Jul 21, 2025 at 2:58 PM Daniel P. Berrangé wrote:
>
> Currently the tracing 'log' back emits special code to add timestamps
> to trace points sent via qemu_log(). This current impl is a bad design
> for a number of reasons.
>
> * It changes the QEMU headers, such that 'error-report.h' con
On Thu, Jul 17, 2025 at 7:57 AM Markus Armbruster wrote:
>
> We recently (merge commit 504632dcc631) enclosed command and type
> names in `backquotes`, so they become links in generated HTML. Take
> care of a few we missed.
>
> Signed-off-by: Markus Armbruster
> ---
> qapi/dump.json | 2 +-
From: Yihao Fan
This patch series introduces basic support for the STM32F407 SoC and
a new STM32F4spark machine in QEMU, along with a USART device model.
This series includes:
- A new SoC model (STM32F407) with initial integration.
- A board model called STM32F4spark to instantiate and test the
From: Yihao Fan
This patch introduces a new QEMU machine type for the STM32F407 SoC featuring a
Cortex-M4 core.
This will be used by the RT-Spark to create a machine.
Signed-off-by: Yihao Fan
---
MAINTAINERS| 7 ++
hw/arm/Kconfig | 6 ++
hw/arm/meson.bu
From: Yihao Fan
Add the STM32F4spark machine model using the STM32F407 SoC.
Signed-off-by: Yihao Fan
---
MAINTAINERS | 7 +++
hw/arm/Kconfig| 6 ++
hw/arm/meson.build| 1 +
hw/arm/stm32f4spark.c | 48 +++
4 files changed,
From: Yihao Fan
This patch adds support for the STM32F407 USART controllers device model.
Signed-off-by: Yihao Fan
---
MAINTAINERS | 2 +
hw/arm/Kconfig| 1 +
hw/arm/stm32f407_soc.c| 25 +++
hw/char/Kconfig | 3 +
h
On Mon, Jul 21, 2025 at 3:04 PM Daniel P. Berrangé wrote:
>
> On Mon, Jul 21, 2025 at 02:10:51PM -0400, Stefan Hajnoczi wrote:
> > From: Vladimir Sementsov-Ogievskiy
> >
> > So tired to parse all these timestamps, when need to compare them
> > with other logs.
> >
> > Use iso8601 format as in war
> On 21 Jul 2025, at 12:39, Jonathan Cameron via wrote:
>
> On Fri, 18 Jul 2025 19:20:42 +0300
> Vadim Chichikalyuk wrote:
>
>> The UART clock frequency field of the SPCR table was added in revision 3.
>> Currently, build_spcr() treats revision 3 tables the same as revision 2 and
>> only incl
From: Zenghui Yu
Commit a2260983c655 ("hvf: arm: Add support for GICv3") added GICv3 support
by implementing emulation for a few system registers. ICC_RPR_EL1 was
defined but not plugged in the sysreg handlers (for no good reason).
Fix it.
Fixes: a2260983c655 ("hvf: arm: Add support for GICv3")
From: Daniel P. Berrangé
When a VNC client sends a "set pixel format" message, the
'client_endian' field will get initialized, however, it is
valid to omit this message if the client wants to use the
server's native pixel format. In the latter scenario nothing
is initializing the 'client_endian'
From: Peter Maydell
We don't implement the Debug Communications Channel (DCC), but
we do attempt to provide dummy versions of its system registers
so that software that tries to access them doesn't fall over.
However, we got the tx/rx register definitions wrong. These
should be:
AArch32:
DBGD
From: Paolo Bonzini
KVM emulates the ARCH_CAPABILITIES on x86 for both Intel and AMD
cpus, although the IA32_ARCH_CAPABILITIES MSR is an Intel-specific
MSR and it makes no sense to emulate it on AMD.
As a consequence, VMs created on AMD with qemu -cpu host and using
KVM will advertise the ARCH_C
The following patches are queued for QEMU stable v10.0.3:
https://gitlab.com/qemu-project/qemu/-/commits/staging-10.0
Patch queue is frozen on 2025-07-21, and the release is planned for 2025-07-23:
https://wiki.qemu.org/Planning/10.0
Please respond here or CC qemu-sta...@nongnu.org on any a
From: Peter Maydell
The transmit loop in gmac_try_send_next_packet() is constructed in a
way that means it will send incorrect data if it it sends more than
one packet.
The function assembles the outbound data in a dynamically allocated
block of memory which is pointed to by tx_send_buffer. We
On 16/07/2025 11:54, Alex Bennée wrote:
We didn't have any reliable way to build sparc test cases. I have
found someone who ships a compiler but the binaries still don't run
due to the need for CASA.
I'm posting mainly for those who actually care who might want to fix
up the remaining cases.
A
On 7/15/25 10:34 PM, Pierrick Bouvier wrote:
This plugin generates a binary trace compatible with the excellent uftrace:
https://github.com/namhyung/uftrace
In short, it tracks all function calls performed during execution, based on
frame pointer analysis. A big advantage over "uftrace record" i
This plugin generates a binary trace compatible with the excellent uftrace:
https://github.com/namhyung/uftrace
In short, it tracks all function calls performed during execution, based on
frame pointer analysis. A big advantage over "uftrace record" is that it works
in system mode, allowing to tra
This documentation summarizes how to use the plugin, and present two
examples of the possibilities offered by it.
As well, it explains how to rebuild and reproduce easily the system boot
example.
Signed-off-by: Pierrick Bouvier
---
docs/about/emulation.rst | 207 +++
This plugin generates a binary trace compatible with:
https://github.com/namhyung/uftrace
It tracks frame pointer during execution, detecting function
calls/returns and works in system and user mode.
It's implemented for aarch64 only (adding other architecture should
be trivial, especially x86_64
usage: timestamp-based-on-real-time=[on|off]
Instead of using number of instructions executed (which is per vcpu), we
use the wall time for timestamps. This is useful when tracing user mode
programs as well.
Signed-off-by: Pierrick Bouvier
---
contrib/plugins/uftrace.c | 29
usage: contrib/plugins/uftrace_symbols.py \
--prefix-symbols \
arm-trusted-firmware/build/qemu/debug/bl1/bl1.elf \
arm-trusted-firmware/build/qemu/debug/bl2/bl2.elf \
arm-trusted-firmware/build/qemu/debug/bl31/bl31.elf \
u-boot/u-boot:0x6000 \
u-
usage: trace-privilege-level=[on|off]
This option generates different traces (represented as different
processes in uftrace), allowing to follow privilege level changes.
For aarch64, we track current EL and Security State.
As well, we make sure that sampling works correctly with this option. If
usage: trace-sample=N
Allow to use sampling (every N instructions) for tracking the stack.
We implement a fast mode, where instrumentation is only per tb, and
simply dump current stack, and unwind new one, instead of tracking every
frame pointer change.
Signed-off-by: Pierrick Bouvier
---
contr
Daniel P. Berrangé writes:
> We want some visibility on stderr when the GNUTLS thread
> safety countermeasures are activated, to encourage people
> to get the real fix deployed (once it exists). Some trace
> points will also help if we see any further wierd crash
> scenario we've not anticipated.
Daniel P. Berrangé writes:
> When TLS 1.3 is negotiated on a TLS session, GNUTLS will perform
> automatic rekeying of the session after 16 million records. This
> is done for all algorithms except CHACHA20_POLY1305 which does
> not require rekeying.
>
> Unfortunately the rekeying breaks GNUTLS' p
On 7/11/25 17:11, Zhuoying Cai wrote:
> Add documentation for secure IPL
>
> Signed-off-by: Collin Walling
> Signed-off-by: Zhuoying Cai
We should consider segmenting these documents by introducing the wording
with the same patch that introduces the relevant functionality. I'll
try to do my be
On Fri, Jul 18, 2025 at 03:20:35PM +0200, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > On Fri, Jul 18, 2025 at 07:59:50AM +0200, Markus Armbruster wrote:
> >> Markus Armbruster writes:
> >>
> >> > Adam Williamson writes:
> >> >
> >> >> In cfcacba an `error_report` was added to t
On Mon, Jul 21, 2025 at 02:10:51PM -0400, Stefan Hajnoczi wrote:
> From: Vladimir Sementsov-Ogievskiy
>
> So tired to parse all these timestamps, when need to compare them
> with other logs.
>
> Use iso8601 format as in warn_report() (info_report(), error_report())
> already used.
>
> Also, sta
Currently the tracing 'log' back emits special code to add timestamps
to trace points sent via qemu_log(). This current impl is a bad design
for a number of reasons.
* It changes the QEMU headers, such that 'error-report.h' content
is visible to all files using tracing, but only when the 'log'
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
signature.asc
Description: PGP signature
On Mon, Jul 21, 2025 at 01:51:44PM +, Bernd Schubert wrote:
> I need test these flags again, might be worthful for qemu as well
>
> /* These flags should help to increase performance, but actually
>* make it a bit slower - reason should get investigated.
>*/
> if (0
On Wed, Jul 02, 2025 at 02:10:45PM +0200, Kevin Wolf wrote:
> Am 20.06.2025 um 02:08 hat Stefan Hajnoczi geschrieben:
> > When an AioHandler is enqueued on ctx->submit_list for removal, the
> > fill_sq_ring() function will submit an io_uring POLL_REMOVE operation to
> > cancel the in-flight POLL_AD
The following changes since commit 56a3033abcfcf72a2f4f1376a605a0b1ad526b67:
Merge tag 'pull-request-2025-07-21' of https://gitlab.com/thuth/qemu into
staging (2025-07-21 06:34:56 -0400)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/tracing-pull-request
From: Vladimir Sementsov-Ogievskiy
So tired to parse all these timestamps, when need to compare them
with other logs.
Use iso8601 format as in warn_report() (info_report(), error_report())
already used.
Also, start line with date, to be similar with warn_report() as well.
Signed-off-by: Vladim
On 7/21/25 10:31 AM, Peter Maydell wrote:
On Mon, 21 Jul 2025 at 18:26, Pierrick Bouvier
wrote:
On 7/21/25 10:14 AM, Michael Tokarev wrote:
rr is the first thing I tried. Nope, it's absolutely hopeless. It
tried to boot just the kernel for over 30 minutes, after which I just
gave up.
I
On Mon, 21 Jul 2025 at 18:26, Pierrick Bouvier
wrote:
>
> On 7/21/25 10:14 AM, Michael Tokarev wrote:
> > rr is the first thing I tried. Nope, it's absolutely hopeless. It
> > tried to boot just the kernel for over 30 minutes, after which I just
> > gave up.
> >
>
> I had a similar thing to deb
On 7/21/25 10:25 AM, Pierrick Bouvier wrote:
On 7/21/25 10:14 AM, Michael Tokarev wrote:
On 21.07.2025 19:29, Pierrick Bouvier wrote:
On 7/21/25 9:23 AM, Pierrick Bouvier wrote:
..
looks like a good target for TSAN, which might expose the race without
really having to trigger it.
https://www.
On 7/21/25 10:14 AM, Michael Tokarev wrote:
On 21.07.2025 19:29, Pierrick Bouvier wrote:
On 7/21/25 9:23 AM, Pierrick Bouvier wrote:
..
looks like a good target for TSAN, which might expose the race without
really having to trigger it.
https://www.qemu.org/docs/master/devel/testing/main.html#b
From: Shiju Jose
Add updates for the CXL spec rev3.2 changes, in the CXL events reporting
and QMP command to inject CXL events.
Add maintenance support and emulation support for memory Post Package
Repair(PPR) and memory sparing control features.
Add support for reporting the memory sparing eve
From: Shiju Jose
Move the declaration of scrub and ECS feature attributes in
cmd_features_set_feature() to the local scope where they are used.
Signed-off-by: Jonathan Cameron
Signed-off-by: Shiju Jose
---
hw/cxl/cxl-mailbox-utils.c | 17 +++--
1 file changed, 7 insertions(+), 10
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
event record has updated with following new fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Add updates for the above spec changes in the CXL memory module
event reporting and QMP command t
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
table has updated with following new fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
4. Support for component ID in
From: Shiju Jose
Memory sparing is defined as a repair function that replaces a portion of
memory with a portion of functional memory at that same DPA. The
subclasses for this operation vary in terms of the scope of the sparing
being performed. The Cacheline sparing subclass refers to a sparing
a
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
has updated with following new fields.
1. Component Identifier
2. Sub-channel of the memory event location
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Volatile Memory Error C
From: Davidlohr Bueso
This adds initial support for the Maintenance command, specifically
the soft and hard PPR operations on a dpa. The implementation allows
to be executed at runtime, therefore semantically, data is retained
and CXL.mem requests are correctly processed.
Keep track of the reque
From: Shiju Jose
CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
format has updated with optional Maintenance Operation Subclass,
LD ID and ID of the device head information.
Add updates for the above optional parameters in the related
CXL events reporting and in the QMP commands
On 21.07.2025 19:29, Pierrick Bouvier wrote:
On 7/21/25 9:23 AM, Pierrick Bouvier wrote:
..
looks like a good target for TSAN, which might expose the race without
really having to trigger it.
https://www.qemu.org/docs/master/devel/testing/main.html#building-and-
testing-with-tsan
I think I t
On 6/27/25 5:24 PM, Pierrick Bouvier wrote:
Depending on host cpu speed, and QEMU optimization level, it may sometimes be
needed to slow or accelerate time guest is perceiving. A common scenario is
hitting a timeout during a boot process, because some operations were not
finished on time.
An exi
On Mon, Jul 21, 2025 at 4:58 PM Peter Maydell wrote:
>
> Ping -- any opinions/review about this one?
>
> -- PMM
>
> On Thu, 10 Jul 2025 at 18:43, Peter Maydell wrote:
> >
> > In framebuffer_update_display(), Coverity complains because we
> > multiply two values of type 'int' (which will be done a
On Mon, Jul 21, 2025 at 6:34 PM Alex Bennée wrote:
>
> This is a simple test case that runs an image with kvmtool and
> kvm-unit-tests which can validate virtualisation works. This is useful
> for exercising TCG but can also be applied to any nested virt setup
> which is why it doesn't specify an
From: Nicholas Piggin
xive2 must take into account redistribution of group interrupts if
the VP directed priority exceeds the group interrupt priority after
this operation. The xive1 code is not group aware so implement this
for xive2.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Re
From: Nicholas Piggin
xive_tctx_pipr_present() as implemented with xive_tctx_pipr_update()
causes VP-directed (group==0) interrupt to be presented in PIPR and NSR
despite being a lower priority than the currently presented group
interrupt.
This must not happen. The IPB bit should record the low
From: Nicholas Piggin
Rather than functions to return masks to test NSR bits, have functions
to test those bits directly. This should be no functional change, it
just makes the code more readable.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Reviewed-by:
From: Nicholas Piggin
Implement set LGS for the POOL ring.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Link:
https://lore.kernel.org/qemu-devel/20250512031100.439842-48-npig...@gmail.com
Signed-off-by: Cédric Le Goater
---
From: Nicholas Piggin
OS-push operation must re-present pending interrupts. Use the
newly created xive2_tctx_process_pending() function instead of
duplicating the logic.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Link:
https
From: Nicholas Piggin
When the pool context is pulled, the shared pool/phys signal is
reset, which loses the qemu irq if a phys interrupt was presented.
Only reset the signal if a poll irq was presented.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Teste
From: Glenn Miles
Add support for XIVE ESB Interrupt Escalation.
Suggested-by: Michael Kowal
[This change was taken from a patch provided by Michael Kowal.]
Signed-off-by: Glenn Miles
Reviewed-by: Nicholas Piggin
Reviewed-by: Michael Kowal
Reviewed-by: Caleb Schlossin
Tested-by: Gautam Meng
From: Glenn Miles
Add more tracing around notification, redistribution, and escalation.
Signed-off-by: Glenn Miles
Reviewed-by: Nicholas Piggin
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Link:
https://lore.kernel.org/qemu-devel/20250512031100.439842-24-npig...@gmail.com
Signed-of
From: Nicholas Piggin
The group interrupt delivery flow selects the group backlog scan if
LSMFB < IPB, but that scan may find an interrupt with a priority >=
IPB. In that case, the VP-direct interrupt should be chosen. This
extends to selecting the lowest prio between POOL and PHYS rings.
Implem
From: Nicholas Piggin
After pulling the pool context, if a pool irq had been presented and
was cleared in the process, there could be a pending irq in phys that
should be presented. Process the phys irq ring after pulling pool ring
to catch this case and avoid losing irqs.
Signed-off-by: Nichola
From: Nicholas Piggin
Have xive_tctx_notify() also set the new PIPR value and rename it to
xive_tctx_pipr_set(). This can replace the last xive_tctx_pipr_update()
caller because it does not need to update IPB (it already sets it).
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewe
From: Nicholas Piggin
The second part of the set CPPR operation is to process (or re-present)
any pending interrupts after CPPR is adjusted.
Split this presentation processing out into a standalone function that
can be used in other places.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Mil
Hi Michael,
On 7/21/25 4:47 AM, Philippe Mathieu-Daudé wrote:
(Cc'ing few more developers)
On 30/5/25 21:20, Michael Tokarev wrote:
Hi!
For quite some time (almost whole day yesterday) I'm trying to find out
what's going on with mmtcg in qemu. There's apparently a race condition
somewhere, l
From: Nicholas Piggin
Further split xive_tctx_pipr_update() by splitting out a new function
that is used to re-compute the PIPR from IPB. This is generally only
used with XIVE1, because group interrputs require more logic.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Mi
From: Glenn Miles
When an XIVE context is pulled while it has an active, unacknowledged
group interrupt, XIVE will check to see if a context on another thread
can handle the interrupt and, if so, notify that context. If there
are no contexts that can handle the interrupt, then the interrupt is
a
From: Nicholas Piggin
Certain TIMA operations should only be performed when a ring is valid,
others when the ring is invalid, and they are considered undefined if
used incorrectly. Add checks for this condition.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
On 7/21/25 9:23 AM, Pierrick Bouvier wrote:
Hi Michael,
On 7/21/25 4:47 AM, Philippe Mathieu-Daudé wrote:
(Cc'ing few more developers)
On 30/5/25 21:20, Michael Tokarev wrote:
Hi!
For quite some time (almost whole day yesterday) I'm trying to find out
what's going on with mmtcg in qemu. The
From: Nicholas Piggin
xive_tctx_pipr_update() is used for multiple things. In an effort
to make things simpler and less overloaded, split out the function
that is used to present a new interrupt to the tctx.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Te
From: Nicholas Piggin
If CPPR is lowered to preclude the pending interrupt, NSR should be
cleared and the qemu_irq should be lowered. This avoids some cases
of supurious interrupts.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Reviewed-by: Caleb Schlossin
From: Nicholas Piggin
Add some assertions to try to ensure presented group interrupts do
not get lost without being redistributed, if they become precluded
by CPPR or preempted by a higher priority interrupt.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
T
From: Nicholas Piggin
When CPPR priority is decreased, pending interrupts do not need to be
re-checked if one is already presented because by definition that will
be the highest priority.
This prevents a presented group interrupt from being lost.
Signed-off-by: Nicholas Piggin
Reviewed-by: Gle
From: Glenn Miles
When disabling (pulling) an xive interrupt context, we need
to redistribute any active group interrupts to other threads
that can handle the interrupt if possible. This support had
already been added for the OS context but had not yet been
added to the pool or physical context.
From: Michael Kowal
Writes to the Flush Control registers were logged as invalid
when they are allowed. Clearing the unsupported want_cache_disable
feature is supported, so don't log an error in that case.
Signed-off-by: Michael Kowal
Reviewed-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Revi
From: Nicholas Piggin
Implement the phys (aka hard) VP push. PowerVM uses this operation.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Link:
https://lore.kernel.org/qemu-devel/20250512031100.439842-49-npig...@gmail.com
Signed-
From: Nicholas Piggin
This is needed by the next patch which will re-send on all lower
rings when pushing a context.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Link:
https://lore.kernel.org/qemu-devel/20250512031100.439842-5
From: Nicholas Piggin
The relationship between an interrupt signaled in the TIMA and the QEMU
irq line to the processor to be 1:1, so they should be raised and
lowered together and "just in case" lowering should be avoided (it could
mask
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
From: Nicholas Piggin
Group interrupts should not be taken from the backlog and presented
if they are precluded by CPPR.
Fixes: 855434b3b8 ("ppc/xive2: Process group backlog when pushing an OS
context")
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Review
From: Nicholas Piggin
When pushing a context, the lower-level context becomes valid if it
had V=1, and so on. Iterate lower level contexts and send them
pending interrupts if they become enabled.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Tested-by: Gau
From: Nicholas Piggin
When pushing a context, any presented group interrupt should be
redistributed before processing pending interrupts to present
highest priority.
This can occur when pushing the POOL ring when the valid PHYS
ring has a group interrupt presented, because they share signal
regi
From: Glenn Miles
Change pregs to pool_regs, for clarity.
[npiggin: split from larger patch]
Signed-off-by: Glenn Miles
Reviewed-by: Nicholas Piggin
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Link:
https://lore.kernel.org/qemu-devel/20250512031100.439842-25-npig...@gmail.com
Sig
From: Nicholas Piggin
Implement pool context push TIMA op.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Link:
https://lore.kernel.org/qemu-devel/20250512031100.439842-45-npig...@gmail.com
Signed-off-by: Cédric Le Goater
---
From: Michael Kowal
In a multi chip environment there will be remote/forwarded VSDs. The check
to find a matching INT controller (XIVE) of the remote block number was
checking the INTs chip number. Block numbers are not tied to a chip number.
The matching remote INT is the one that matches the
From: Nicholas Piggin
In preparation to implement POOL context push, add support for POOL
NVP context save/restore.
The NVP p bit is defined in the spec as follows:
If TRUE, the CPPR of a Pool VP in the NVP is updated during store of
the context with the CPPR of the Hard context it was
From: Glenn Miles
Add support for redistributing a presented group interrupt if it
is precluded as a result of changing the CPPR value. Without this,
group interrupts can be lost.
Signed-off-by: Glenn Miles
Reviewed-by: Nicholas Piggin
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Li
From: Nicholas Piggin
This improves the implementation of pulling pool and phys contexts in
XIVE1, by following closer the OS pulling code.
In particular, the old ring data is returned rather than the modified,
and irq signals are reset on pull.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glen
From: Michael Kowal
This can make it easier to see what the target system is trying to
do.
[npiggin: split from larger patch]
Signed-off-by: Michael Kowal
Reviewed-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Reviewed-by: Caleb Schlossin
Tested-by: Gautam Menghan
From: Nicholas Piggin
The tctx "signaling" registers (PIPR, CPPR, NSR) raise an interrupt on
the target CPU thread. The POOL and PHYS rings both raise hypervisor
interrupts, so they both share one set of signaling registers in the
PHYS ring. The PHYS NSR register contains a field that indicates w
From: Glenn Miles
Adds support for extracting additional configuration flags from
the XIVE configuration register that are needed for redistribution
of group interrupts.
Signed-off-by: Glenn Miles
Reviewed-by: Nicholas Piggin
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Link:
https
From: Nicholas Piggin
Have the match_nvt method only perform a TCTX match but don't present
the interrupt, the caller presents. This has no functional change, but
allows for more complicated presentation logic after matching.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by:
From: Nicholas Piggin
A group interrupt that gets preempted by a higher priority interrupt
delivery must be redistributed otherwise it would get lost.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-by: Michael Kowal
Tested-by: Gautam Menghani
Link:
https://lore.kernel.org/
From: Glenn Miles
Booting AIX in a PowerVM partition requires the use of the "Acknowledge
O/S Interrupt to even O/S reporting line" special operation provided by
the IBM XIVE interrupt controller. This operation is invoked by writing
a byte (data is irrelevant) to offset 0xC10 of the Thread Inter
From: Nicholas Piggin
Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC
register, so don't clear it on read.
Don't bother clearing the reads-as-zero CONFLICT bit because it's masked
at write already.
Signed-off-by: Nicholas Piggin
Reviewed-by: Glenn Miles
Reviewed-b
From: Glenn Miles
A problem was seen where uart interrupts would be lost resulting in the
console hanging. Traces showed that a lower priority interrupt was
preempting a higher priority interrupt, which would result in the higher
priority interrupt never being handled.
The new interrupt's priori
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