On Wed, 9 Jul 2025 at 01:30, Eric Auger wrote:
> Add a subsection to migrate the AcpiPciHpState state.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Igor Mammedov
> Reviewed-by: Jonathan Cameron
> ---
> hw/acpi/generic_event_device.c | 20
> 1 file changed, 20 insertions(+)
On 9/7/25 22:57, Thomas Weißschuh wrote:
The Linux kernel dropped support for sa_restorer on O32 MIPS in the
release 2.5.48 because it was unused. See the comment in
arch/mips/include/uapi/asm/signal.h.
Applications using the kernels UAPI headers will not reserve enough
space for qemu-user to co
Jonah Palmer writes:
[...]
>> I think I finally know enough to give you constructive feedback.
>>
>> Your commit messages should answer the questions I had. Specifically:
>>
>> * Why are we doing this? To shorten guest-visible downtime.
>>
>> * How are we doing this? We additionally pin me
Hi,
On Wed, Mar 12, 2025 at 03:55:47PM +, Paolo Savini wrote:
> This commit improves the performance of QEMU when emulating strided vector
> loads and stores by substituting the call for the helper function with the
> generation of equivalent TCG operations.
>
> Signed-off-by: Paolo Savini
>
Gpa is defined in QAPI but never reported to monitor because has_gpa is
never set to ture.
Fix it by setting has_gpa to ture when TDX_REPORT_FATAL_ERROR_GPA_VALID
is set in error_code.
Fixes: 6e250463b08b ("i386/tdx: Wire TDX_REPORT_FATAL_ERROR with GuestPanic
facility")
Signed-off-by: Zhenzhong
On 7/9/2025 11:02 PM, Moger, Babu wrote:
Hi Boris,
On 7/9/25 05:49, Borislav Petkov (AMD) wrote:
Hi,
I *think* this is how it should be done but I might be forgetting something.
It seems to work in my testing here.
Babu, double-check me pls.
Thx.
Patch looks good. Few comments.
Is KVM aw
On 2025/7/3 下午5:26, Song Gao wrote:
implement the read-clear feature for CSR_MSGIR register.
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 22 +++
target/loongarch/tcg/helper.h
On 2025/7/3 下午5:26, Song Gao wrote:
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
and CSR_ECFG.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
target/loongarch/cpu.c | 10 ++
2 files changed, 14 insertions(+), 2 delet
On 2025/7/3 下午5:26, Song Gao wrote:
Implement avec set irq and update CSR_MSIS.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
On 2025/7/3 下午5:26, Song Gao wrote:
Add write misc avecintc status bit and read avecintc feature and status bit.
Add feature register and misc register for avecintc feature checking and
setting?
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insert
On 2025/7/3 下午5:26, Song Gao wrote:
LoongArchVirtMachinState add avecintc features, and
it use to check whether virt machine support advance interrupt controller
and default set avecintc = ON_OFF_AUTO_ON.
LoongArchVirtMachineState add misc_feature and misc_status for
misc fetures and status. a
On 2025/7/3 下午5:26, Song Gao wrote:
move some machine define to virt.h
Signed-off-by: Song Gao
---
include/hw/loongarch/virt.h | 19 +++
target/loongarch/cpu.h | 21 -
2 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/include/hw/loo
On 7/9/25 3:20 PM, Nicolin Chen wrote:
On Wed, Jul 09, 2025 at 01:55:46PM -0400, Donald Dutile wrote:
+enum {
+VIOMMU_CAP_STAGE1 = BIT_ULL(0), /* stage1 page table supported */
+};
Thanks for this work. I am happy to see that we can share the
common code that allocates a NESTING_PARENT
On Wed, Jul 09, 2025 at 08:20:35AM +, Shameerali Kolothum Thodi wrote:
> > On Tue, Jul 08, 2025 at 04:40:50PM +0100, Shameer Kolothum wrote:
> > > @@ -2909,6 +2909,19 @@ static void
> > pci_device_get_iommu_bus_devfn(PCIDevice *dev,
> > > }
> > > }
> > >
> > > +/*
On Wed, Jul 09, 2025 at 08:08:49AM +, Shameerali Kolothum Thodi wrote:
> > On Tue, Jul 08, 2025 at 04:40:45PM +0100, Shameer Kolothum wrote:
> > > @@ -937,11 +939,32 @@ static void smmu_base_realize(DeviceState
> > *dev, Error **errp)
> > > g_free, g_free);
-/* ??? This is always present, but ignored unless O32. */
-abi_ulong sa_restorer;
-#endif
};
#else
struct target_old_sigaction {
---
base-commit: df6fe2abf2e990f767ce755d426bc439c7bba336
change-id: 20250709-mips-sa-restorer-42943dfab13b
Best regards,
--
Thomas Weißschuh
On 7/9/25 12:03, Gustavo Romero wrote:
At this point, no real memory encryption is supported, but most software
stacks that rely on FEAT_MEC to run should work properly.
s/most //?
Anyway,
Reviewed-by: Richard Henderson
r~
On 7/9/25 12:03, Gustavo Romero wrote:
This commit implements the two cache maintenance instructions introduced
by FEAT_MEC, DC CIPAE and DC CIGDPAE.
Because QEMU does not model the cache topology, all cache maintenance
instructions are implemented as NOPs, hence these new instructions are
imple
On 7/9/25 12:03, Gustavo Romero wrote:
Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers.
These registers are extensions of the TCR_ELx registers and provide
top-level control of the EL10 and EL20 translation regimes.
Since the bits in these registers depend on other CPU featur
On 7/9/25 12:03, Gustavo Romero wrote:
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 552d8757b7..44d6b655a9 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -416,6 +416,11 @@ static inline bool isar_feature_aa64_rdm(const
ARMISARegisters *id)
On 7/9/25 12:03, Gustavo Romero wrote:
@@ -7816,6 +7818,78 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
.resetvalue = 0 },
};
+static CPAccessResult sctlr2_el2_access(CPUARMState *env,
+const ARMCPRegInfo *ri,
+
On Wed, Jul 9, 2025, 3:40 PM Paolo Bonzini wrote:
>
>
> Il mer 9 lug 2025, 20:39 John Snow ha scritto:
>
>> You are right. However, the mkvenv configuration tool we pioneered has
>> been largely un-noticed by contributors and appears to "just work" for
>> the last several years. I believe that c
On 7/9/25 12:03, Gustavo Romero wrote:
Add all FEAT_MEC registers.
To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2,
which are not implemented in this commit. The bits in SCTLR2 and TCR2
control which translation regimes use MECIDs, and determine which MECID
is selected.
FEA
On 7/8/25 4:17 AM, Markus Armbruster wrote:
Jonah Palmer writes:
On 7/4/25 11:00 AM, Markus Armbruster wrote:
Jonah Palmer writes:
[...]
So, total time increases: early pinning (before main loop) takes more
time than we save pinning (in the main loop). Correct?
Correct. We only sav
Il mer 9 lug 2025, 20:39 John Snow ha scritto:
> You are right. However, the mkvenv configuration tool we pioneered has
> been largely un-noticed by contributors and appears to "just work" for
> the last several years. I believe that cost has been *largely*
> amortized by yours truly, and I have
On Wed, Jul 09, 2025 at 01:55:46PM -0400, Donald Dutile wrote:
> > > +enum {
> > > +VIOMMU_CAP_STAGE1 = BIT_ULL(0), /* stage1 page table supported */
> > > +};
> >
> > Thanks for this work. I am happy to see that we can share the
> > common code that allocates a NESTING_PARENT in the core usi
Hello,
I am working with an SoC that only supports NVMe, and would like to be able to
savevm/loadvm, and maybe also record/replay.
The NVMe has a VMStateDescription with just unmigratable = 1 ever since it was
first added in 2013.
Is there a technical or other limitation/reason for why this is t
Reviewed-by: Jared Rossi
On 7/9/25 4:34 AM, Thomas Huth wrote:
From: Thomas Huth
Show a simple boot menu for pxelinux.cfg, too, if the user requested it.
Signed-off-by: Thomas Huth
---
pc-bios/s390-ccw/netmain.c | 26 ++
1 file changed, 26 insertions(+)
diff --gi
Reviewed-by: Jared Rossi
On 7/9/25 4:34 AM, Thomas Huth wrote:
From: Thomas Huth
We are going to reuse this function for selecting an entry from
the pxelinux.cfg menu, so rename this function with a "menu_"
prefix and make it available globally.
Signed-off-by: Thomas Huth
---
pc-bios/s390
Reviewed-by: Jared Rossi
On 7/9/25 4:34 AM, Thomas Huth wrote:
From: Thomas Huth
Check the various ways of booting a kernel via pxelinux.cfg file,
e.g. by specifying the config file name via the MAC address or the
UUID of the guest. Also check whether we can successfully load an
alternate ker
Reviewed-by: Jared Rossi
On 7/9/25 4:34 AM, Thomas Huth wrote:
From: Thomas Huth
Since we're linking the network booting code into the main firmware
binary nowadays, we can support the "loadparm" parameter now quite
easily for pxelinux.cfg config files that contain multiple entries.
Signed-o
Reviewed-by: Jared Rossi
On 7/9/25 4:34 AM, Thomas Huth wrote:
From: Thomas Huth
We're going to support a menu for the pxelinux.cfg code, and to be able
to reuse some functionality from menu.c, we should align the maximum
amount of possible entries with the MAX_BOOT_ENTRIES constant that is
u
On Mon, Jul 7, 2025 at 5:11 AM Daniel P. Berrangé wrote:
>
> On Wed, Jul 02, 2025 at 03:24:09PM -0400, Paolo Bonzini wrote:
> > Il mar 24 giu 2025, 02:45 Markus Armbruster ha scritto:
> >
> > > > ... I think I value this a bit higher than Markus, but not really
> > > because of offline builds. R
On 7/8/25 13:17, Gustavo Romero wrote:
Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and
SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx
ones.
Because the bits in these registers depend on other CPU features, and
only FEAT_MEC is supported at the moment, thi
Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and
SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx
ones.
Because the bits in these registers depend on other CPU features, and
only FEAT_MEC is supported at the moment, this commit only implements
the EMEC bits in
Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a
first step to fully support FEAT_MEC.
The FEAT_MEC is an extension to FEAT_RME that implements multiple
Memory Encryption Contexts (MEC) so the memory in a realm can be
encrypted and accessing it from the wrong encryption conte
Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers.
These registers are extensions of the TCR_ELx registers and provide
top-level control of the EL10 and EL20 translation regimes.
Since the bits in these registers depend on other CPU features, and only
FEAT_MEC is supported at the
Add all FEAT_MEC registers.
To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2,
which are not implemented in this commit. The bits in SCTLR2 and TCR2
control which translation regimes use MECIDs, and determine which MECID
is selected.
FEAT_MEC also requires two new cache managem
The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from
EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu
This commit implements the two cache maintenance instructions introduced
by FEAT_MEC, DC CIPAE and DC CIGDPAE.
Because QEMU does not model the cache topology, all cache maintenance
instructions are implemented as NOPs, hence these new instructions are
implemented as NOPs too.
Signed-off-by: Gusta
This series adds support for all FEAT_MEC registers and cache instructions to
the arm64 max CPU.
It includes the FEAT_MEC registers and cache maintenance instructions, but does
not modify the translation regimes to support the MECIDs, so no encryption is
supported yet. However, most software stack
On 7/8/25 8:39 PM, Nicolin Chen wrote:
On Tue, Jul 08, 2025 at 07:05:43AM -0400, Zhenzhong Duan wrote:
diff --git a/include/hw/iommu.h b/include/hw/iommu.h
new file mode 100644
index 00..e80aaf4431
--- /dev/null
+++ b/include/hw/iommu.h
@@ -0,0 +1,16 @@
+/*
+ * General vIOMMU capabili
Top-posting (Gasp!) to share a gitlab URL where this script is now located.
https://gitlab.com/jsnow/repology-dashboard#
GPL2.0-or-later, barely polished, a bit hacky. Have fun! This script
outputs more data than you've ever wanted to stdout, json and csv.
Suggestions/patches welcome if you find
On 7/4/25 4:19 PM, Cornelia Huck wrote:
> Fixes: 804cfc7eedb7 ("arm/cpu: Store aa64isar0/aa64zfr0 into the idregs
> arrays")
> Signed-off-by: Cornelia Huck
Reviewed-by: Eric Auger
Eric
> ---
> target/arm/kvm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/targ
On 7/4/25 4:19 PM, Cornelia Huck wrote:
> Signed-off-by: Cornelia Huck
Reviewed-by: Eric Auger
Eric
> ---
> hw/intc/armv7m_nvic.c| 2 +-
> target/arm/cpu-sysregs.h.inc | 1 +
> target/arm/cpu.h | 3 +--
> target/arm/cpu64.c | 4 ++--
> target/arm/helper.c
On 7/4/25 4:19 PM, Cornelia Huck wrote:
> While a trailing comma is not broken for SET_IDREG invocations, it
> does look odd; use a semicolon instead.
>
> Fixes: f1fd81291c91 ("arm/cpu: Store aa64mmfr0-3 into the idregs array")
> Fixes: def3f1c1026a ("arm/cpu: Store aa64dfr0/1 into the idregs ar
On 7/4/25 4:19 PM, Cornelia Huck wrote:
> Signed-off-by: Cornelia Huck
Reviewed-by: Eric Auger
Eric
> ---
> target/arm/cpu-sysregs.h.inc | 2 ++
> target/arm/cpu.h | 2 --
> target/arm/helper.c | 4 ++--
> target/arm/tcg/cpu64.c | 16
> 4 files
Hi Connie,
On 7/4/25 4:19 PM, Cornelia Huck wrote:
> Signed-off-by: Cornelia Huck
Reviewed-by: Eric Auger
Eric
> ---
> hw/intc/armv7m_nvic.c| 2 +-
> target/arm/cpu-sysregs.h.inc | 1 +
> target/arm/cpu.h | 1 -
> target/arm/cpu64.c | 4 ++--
> target/arm/help
On 7/9/2025 4:39 AM, Markus Armbruster wrote:
Steve Sistare writes:
Define the qom-list-getv command, which fetches all the properties and
values for a list of paths. This is faster than qom-tree-get when
fetching a subset of the QOM tree. See qom.json for details.
Signed-off-by: Steve Sist
On 7/8/2025 6:02 PM, Philippe Mathieu-Daudé wrote:
Hi Steve,
On 8/7/25 19:24, Steve Sistare wrote:
Add a unit test for qom-list-getv.
Signed-off-by: Steve Sistare
---
tests/qtest/qom-test.c | 64 ++
1 file changed, 64 insertions(+)
diff --gi
On Mon, Jul 07, 2025 at 07:20:04PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Mon, 7 Jul 2025 19:20:04 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH-for-10.1 v6 10/14] hw/core/null-machine: Define machine as
> generic QOM type
> X-Mailer: git-send-email 2.49.0
>
> While DEFINE_MACHIN
Hi Boris,
On 7/9/25 05:49, Borislav Petkov (AMD) wrote:
> Hi,
>
> I *think* this is how it should be done but I might be forgetting something.
> It seems to work in my testing here.
>
> Babu, double-check me pls.
>
> Thx.
Patch looks good. Few comments.
Is KVM aware of these bits? I didn’t n
On Mon, Jul 07, 2025 at 07:19:56PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Mon, 7 Jul 2025 19:19:56 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH-for-10.1 v6 02/14] qemu/target-info: Factor target_arch()
> out
> X-Mailer: git-send-email 2.49.0
>
> To keep "qemu/target-info.h" self
On 07.07.25 06:49, Jason Wang wrote:
On Thu, Jul 3, 2025 at 10:59 PM Daniil Tatianin
wrote:
On 7/3/25 1:55 PM, Vladimir Sementsov-Ogievskiy wrote:
Theoretically tap_read_packet() may return size less than
s->host_vnet_hdr_len, and next, we'll work with negative size
(in case of !s->using_vne
Rot127 writes:
> From 6c116b968cb28bcc0d0236913f1926206f50a9b4 Mon Sep 17 00:00:00 2001
> From: Rot127
> Date: Fri, 27 Jun 2025 04:51:25 -0500
> Subject: [PATCH] Adds the GDB register XML files for Sparc and
> Sparc64.
These seems like a mangled commit. I can't get it to apply cleanly with
eit
ping:)
On 03.07.25 15:47, Vladimir Sementsov-Ogievskiy wrote:
This field is mostly unused and sometimes confusing (we even have
a TODO-like comment to drop it). Let's finally do.
Vladimir Sementsov-Ogievskiy (4):
vhost: introduce vhost_ops->vhost_set_vring_enable_supported method
vhost-us
Sphinx supports the :kbd: role for notating keyboard input. They get
formatted as HTML elements in the readthedocs theme we currently
use for Sphinx.
Besides the better visual formatting, it also helps with accessibility
as screen readers can announce the semantics of the element to the
user.
S
On Wed, Jul 09, 2025 at 03:34:20PM +0200, Philippe Mathieu-Daudé wrote:
> Hi Gerd,
>
> On 9/7/25 14:30, Gerd Hoffmann wrote:
> > Implement a ConfidentialGuestSupportClass for non-confidential VMs.
> > This allows the igvm support code work without sev/tdx.
>
> Is this something we only want in no
On 7/8/25 10:10, Peter Maydell wrote:
You could argue that the fallback-to-libc-fchmodat here isn't
worth bothering with, I guess.
Indeed not. Support for fchmodat2 is at least 2 years old already.
r~
On 7/8/25 05:52, Peter Maydell wrote:
The GIC distributor registers GICD_TYPER2 is present when the
GICv4.1 is implemented, and RES0 otherwise. QEMU's TCG implementation
is only GICv4.0, so this register is RES0. However, since it's
reasonable for GICv4.1-aware software to read the register, expe
On 7/8/25 05:52, Peter Maydell wrote:
We don't generally like DPRINTF debug macros, preferring tracepoints.
In this case the macro is used in only three places (reset, realize,
and in the unlikely event the host kernel doesn't have GICv3 register
access support). These don't seem worth converting
Hi Gerd,
On 9/7/25 14:30, Gerd Hoffmann wrote:
Implement a ConfidentialGuestSupportClass for non-confidential VMs.
This allows the igvm support code work without sev/tdx.
Is this something we only want in non-KVM builds due to security
boundary concerns?
RfC: Not fully sure this is the best
On 7/4/25 3:05 PM, Daniel Borkmann wrote:
> Extend 'inhibit=on' setting with the option to specify a pinned XSK map
> path along with a starting index (default 0) to push the created XSK
> sockets into. Example usage:
>
> # ./build/qemu-system-x86_64 [...] \
>-netdev
> af-xdp,ifname=enp2s0f
Implement a ConfidentialGuestSupportClass for non-confidential VMs.
This allows the igvm support code work without sev/tdx.
RfC: Not fully sure this is the best way to implement this.
Alternatively we could add this directly into the igvm backend and run
it in case no confidential guest support ob
Thanks to 72d277a7, 1ed2cb32, and others, EDID (Extended Display
Identification Data) is propagated by QEMU such that a virtual display
presents legitimate metadata (e.g., name, serial number, preferred
resolutions, etc.) to its connected guest.
This change adds the ability to specify the EDID nam
Thanks to 72d277a7, 1ed2cb32, and others, EDID (Extended Display
Identification Data) is propagated by QEMU such that a virtual display
presents legitimate metadata (e.g., name, serial number, preferred
resolutions, etc.) to its connected guest.
This change adds the ability to specify the EDID nam
Manos Pitsidianakis writes:
> Sphinx supports the :kbd: role for notating keyboard input. They get
> formatted as HTML elements in the readthedocs theme we currently
> use for Sphinx.
>
> Besides the better visual formatting, it also helps with accessibility
> as screen readers can announce the
On 7/4/25 3:05 PM, Daniel Borkmann wrote:
> While testing, it turned out that upon error in the queue creation loop,
> we never trigger the af_xdp_cleanup() handler. This is because we pass
> errp instead of a local err pointer into the various AF_XDP setup functions
> instead of a scheme like:
>
On 7/4/25 3:05 PM, Daniel Borkmann wrote:
> There are two issues with the XDP program removal in af_xdp_cleanup():
>
> 1) Starting from libxdp 1.3.0 [0] the XDP program gets automatically
>detached when we call xsk_socket__delete() for the last successfully
>configured queue. libxdp intern
Hi Mark,
On 9/7/25 09:50, Mark Cave-Ayland wrote:
On 18/06/2025 07:12, Mark Cave-Ayland wrote:
This series contains a few minor tidy-ups along with an implementation
of the
logic to only allow ESP commands permitted in the current mode. The
motivation
is to fix GitLab issue #2464 which causes
On 18/6/25 08:12, Mark Cave-Ayland wrote:
Whilst working on the previous patch, the existing comment was not enough to
document when the TI command codepath was being used. Update and improve the
comment accordingly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 5 +++--
1 file changed
On 18/6/25 08:12, Mark Cave-Ayland wrote:
In the cases where mixed DMA/non-DMA transfers are used or no data is
available, it is possible to for the calculated transfer length to be
zero. Only call the dma_memory_write function where the transfer length
is non-zero to avoid invoking the DMA engin
On 18/6/25 08:12, Mark Cave-Ayland wrote:
In the cases where mixed DMA/non-DMA transfers are used or no data is
available, it is possible to for the calculated transfer length to be
"to ~for~ the..."
zero. Only call the dma_memory_read function where the transfer length
is non-zero to avoid i
On 18/6/25 08:12, Mark Cave-Ayland wrote:
This is not needed as it is now handled by the OBJECT_DECLARE_SIMPLE_TYPE()
macro.
Signed-off-by: Mark Cave-Ayland
---
include/hw/scsi/esp.h | 2 --
1 file changed, 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 18/6/25 08:12, Mark Cave-Ayland wrote:
Clarify the logic in esp_transfer_data() to ensure that the deferred interrupt
code
can only be triggered for CMD_SEL, CMD_SELATN and CMD_TI commands. This should
already
be the case, but make it explicit to ensure the logic isn't triggered
unexpectedl
John Snow writes:
> On Tue, Jul 8, 2025, 7:23 PM Paolo Bonzini wrote:
>
>> On 7/8/25 22:36, John Snow wrote:
>> > centos_stream_9 3.9.23 21.3.1 53.0.0 3.4.3 BaseOS, CRB
>>
>> Ok, so the lowest version of Sphinx (3.4.3) is currently used for CentOS
>> Stream 9. It's supported for r
Hi,
I *think* this is how it should be done but I might be forgetting something.
It seems to work in my testing here.
Babu, double-check me pls.
Thx.
---
Add CPUID leaf 0x8000_0021.ECX support and add the TSA CPUID flags.
Signed-off-by: Borislav Petkov (AMD)
---
target/i386/cpu.c | 20 +
Marc-André Lureau writes:
> Hi
>
> On Tue, Jul 8, 2025 at 9:07 PM Andrew Keesler wrote:
>>
>> Thanks to 72d277a7, 1ed2cb32, and others, EDID (Extended Display
>> Identification Data) is propagated by QEMU such that a virtual display
>> presents legitimate metadata (e.g., name, serial number, pre
On 7/1/25 2:00 AM, dbarb...@ventanamicro.com wrote:
> > From: Xuemei Liu
> >
> > This adds powerdown support by implementing the ACPI GED.
> >
> > Signed-off-by: Xuemei Liu
> > Co-authored-by: Björn Töpel
> >
> > ---
> > Changes in v3:
> > - Added missing param to virt_is_acpi_enabled
> > - F
Am 3. Juli 2025 14:20:22 UTC schrieb Manos Pitsidianakis
:
>This is a new lint introduced in Rust 1.88. It does not affect
>compilation when using a previous version or our MSRV, 1.77. But with
>1.88 compilation fails because we deny all warnings:
>
> error: unnecessary transmute
> --> rus
Am 9. Juli 2025 06:22:11 UTC schrieb Manos Pitsidianakis
:
>Hi Bernhard,
>
>Thanks for your patch!
>
>There was an identical patch last week on the list:
>https://lore.kernel.org/qemu-rust/20250703-rust_bindings_allow_unnecessary_transmutes-v1-1-692ca210d...@linaro.org/
>
Oh, I missed it. I ju
On 08/07/2025 16:49, John Levon wrote:
Coverity reported:
CID 1611805: Uninitialized variables
in vfio_user_dma_map(). This can occur in the happy path when
->async_ops was not set; as this doesn't typically happen, it wasn't
caught during testing.
Align both map and unmap implementat
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Steve Sistare writes:
> Define the qom-list-getv command, which fetches all the properties and
> values for a list of paths. This is faster than qom-tree-get when
> fetching a subset of the QOM tree. See qom.json for details.
>
> Signed-off-by: Steve Sistare
You cover letter explains *why* we
From: Thomas Huth
We're going to support a menu for the pxelinux.cfg code, and to be able
to reuse some functionality from menu.c, we should align the maximum
amount of possible entries with the MAX_BOOT_ENTRIES constant that is
used there. Thus replace MAX_PXELINUX_ENTRIES with MAX_BOOT_ENTRIES.
From: Thomas Huth
Check the various ways of booting a kernel via pxelinux.cfg file,
e.g. by specifying the config file name via the MAC address or the
UUID of the guest. Also check whether we can successfully load an
alternate kernel via the "loadparm" parameter here and whether the
boot menu sho
From: Thomas Huth
Show a simple boot menu for pxelinux.cfg, too, if the user requested it.
Signed-off-by: Thomas Huth
---
pc-bios/s390-ccw/netmain.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/pc-bios/s390-ccw/netmain.c b/pc-bios/s390-ccw/netmain.c
index 6f6
Since we're linking the network booting code into the main s390-ccw.img
firmware binary nowadays, we can support the "loadparm" parameter now
quite easily for pxelinux.cfg config files that contain multiple entries,
and also add support for a simple boot menu here.
v2:
- Abort the boot process if
From: Thomas Huth
Since we're linking the network booting code into the main firmware
binary nowadays, we can support the "loadparm" parameter now quite
easily for pxelinux.cfg config files that contain multiple entries.
Signed-off-by: Thomas Huth
---
pc-bios/s390-ccw/netmain.c | 32 ++
From: Thomas Huth
We are going to reuse this function for selecting an entry from
the pxelinux.cfg menu, so rename this function with a "menu_"
prefix and make it available globally.
Signed-off-by: Thomas Huth
---
pc-bios/s390-ccw/s390-ccw.h | 1 +
pc-bios/s390-ccw/menu.c | 6 +++---
2 fil
The code to set the link status is currently located in
qmp_set_link(). This function identifies the device by name,
searches for the corresponding NetClientState, and then updates
the link status.
In some parts of the code, such as vhost-user.c, the
NetClientState are already available. Calling q
The get_vhost_net() function previously contained a large switch
statement to find the VHostNetState pointer based on the net
client's type. This created a tight coupling, requiring the generic
vhost layer to be aware of every specific backend that supported
vhost, such as tap, vhost-user, and vhos
This commit refactors how the maximum transmit queue size for
virtio-net devices is determined, making the mechanism more generic
and extensible.
Previously, virtio_net_max_tx_queue_size() contained hardcoded
checks for specific network backend types (vhost-user and
vhost-vdpa) to determine their
This series introduces support for passt as a new network backend for
QEMU.
The purpose of this new backend is to help to use passt daemon as
easily as the user backend ('-nic passt' as we have '-nic user').
All the passt functionalities will not be available to keep it simple,
and the goal is not
Introduce a boolean is_vhost_user field to the vhost_net
structure. This flag is initialized during vhost_net_init based
on whether the backend is vhost-user.
This refactoring simplifies checks for vhost-user specific behavior,
replacing direct comparisons of 'net->nc->info->type' with the new
fla
This patch continues the effort to decouple the generic vhost layer
from specific network backend implementations.
Previously, the vhost_net initialization code contained a hardcoded
check for the vhost-user client type to retrieve its acked features
by calling vhost_user_get_acked_features(). Thi
This commit introduces a save_acked_features function pointer to
vhost_net and converts the vhost_net function into a generic dispatcher.
The vhost-user backend provides the callback, making its function static.
With this change, no other module has a direct dependency on the
vhost-user implementa
This is a cosmetic change with no functional impact.
The function vhost_set_vring_enable() is specific to vhost_net and
is used outside of vhost_net.c (specifically, in
hw/net/virtio-net.c). To prevent confusion with other similarly named
vhost functions, such as the one found in cryptodev-vhost.c
To prepare for the implementation of '-net passt', this patch moves
the generic stream handling functions from net/stream.c into new
net/stream_data.c and net/stream_data.h files.
This refactoring introduces a NetStreamData struct that encapsulates
the generic fields and logic previously in NetStr
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