Re: [PATCH] migration: add FEATURE_SEEKABLE to QIOChannelBlock

Hi, On Fri, 4 Apr 2025 at 17:35, Marco Cavenati wrote: > The QIO_CHANNEL_FEATURE_SEEKABLE flag is set to indicate that > the channel supports seekable operations. This flag is more about > signaling capability rather than dictating the use of the specific > lseek(2) function. * Yes. > In this c

Re: [PATCH for-10.1 v2 06/37] vfio: Introduce a new header file for internal migration services

On 3/31/25 14:23, Avihai Horon wrote: On 26/03/2025 9:50, Cédric Le Goater wrote: External email: Use caution opening links or attachments Gather all VFIO migration related declarations into "vfio-migration-internal.h" to reduce exposure of VFIO internals in "hw/vfio/vfio-common.h". Cc: Kirt

Re: [PATCH-for-10.0 1/3] tests/functional: Add test for imx8mp-evk board with USDHC coverage

Hi! On 05/04/2025 23.48, Bernhard Beschow wrote: Introduce a functional test which boots Debian 12 on the imx8mp-evk board. Since the root filesystem resides on an SD card, the test also verifies the basic operation of the USDHC. Signed-off-by: Bernhard Beschow --- MAINTAINERS

[PULL 1/1] docs: deprecate RISC-V default machine option

From: Daniel Henrique Barboza Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and made it default for qemu-system-riscv32/64. It was the first RISC-V machine added in QEMU so setting it as default was sensible. Today we have 7 riscv64 and 6 riscv32 machines and having 'spike'

[PULL 0/1] riscv-to-apply queue

The following changes since commit 53f3a13ac1069975ad47cf8bd05cc96b4ac09962: Merge tag 'pull-tcg-20250403' of https://gitlab.com/rth7680/qemu into staging (2025-04-04 10:23:17 -0400) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-2025

Re: [PATCH] hw/pci-bridge/pci_expander_bridge: Fix HDM passthrough condition

Ping Only if (dsp_count==1 && hdm_for_passthrough==true), the QEMU shouldn't implement the HDM decodder for the Host-bridge. But previous code didn't follow this. Thanks Zhijian On 23/03/2025 16:04, Li Zhijian wrote: > Reverse the logical condition for HDM passthrough support in > pci_expander

Re: [PATCH] Revert "virtio-net: Copy received header to buffer"

On Fri, Apr 4, 2025 at 11:19 PM Antoine Damhet wrote: > > This reverts commit 7987d2be5a8bc3a502f89ba8cf3ac3e09f64d1ce. > > The goal was to remove the need to patch the (const) input buffer > with a recomputed UDP checksum by copying headers to a RW region and > inject the checksum there. The patc

Re: [PATCH] virtio-net: Copy all for dhclient workaround

On Sat, Apr 5, 2025 at 4:04 PM Akihiko Odaki wrote: > > The goal of commit 7987d2be5a8b ("virtio-net: Copy received header to > buffer") was to remove the need to patch the (const) input buffer with a > recomputed UDP checksum by copying headers to a RW region and inject the > checksum there. The

[PATCH v2] target/i386: Fix model number of Zhaoxin YongFeng vCPU template

The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4. The correct value is 0x5b. This mistake occurred because the extended model bits in cpuid[eax=0x1].eax were overlooked, and only the base model was used. This patch corrects the model field. Fixes: ff04bc1ac4 ("target/i386: In

Re: [PATCH 2/2] hw/riscv/virt.c: change default CPU to 'max'

On Sat, Apr 5, 2025 at 9:02 AM Richard Henderson wrote: > > On 4/4/25 08:27, Daniel Henrique Barboza wrote: > > Using 'max' as > > default CPU is done by other QEMU archs like aarch64 so we'll be more > > compatible with everyone else. > > This isn't true. qemu-system-aarch64 -M virt defaults to

Re: [PATCH for-10.0] docs: deprecate RISC-V default machine option

On Fri, Apr 4, 2025 at 10:30 PM Daniel Henrique Barboza wrote: > > Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and > made it default for qemu-system-riscv32/64. It was the first RISC-V > machine added in QEMU so setting it as default was sensible. > > Today we have 7 riscv6

Re: [PATCH 1/2] target/riscv/tcg: make 'max' cpu rva23s64 compliant

On Sat, Apr 5, 2025 at 1:29 AM Daniel Henrique Barboza wrote: > > The 'max' CPU includes all available extensions we implement, but at > this moment it is not rva23s64 compliant due to missing checks that > the parent profile (rva22s64) does. > > Users might expect that the a CPU called 'max' CPU

Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target

On Mon, Apr 7, 2025 at 4:24 AM Frédéric Pétrot wrote: > > Hi Alistair, Phil, > well, I'm trying to keep the thing alive, checking from time to time that > the current QEMU still runs the 128-bit tests that I have, and on which > I continue (slowly) to do stuffs. If it's being used then I don't se

Re: [PATCH for-10.0] docs: deprecate RISC-V default machine option

On Fri, Apr 4, 2025 at 10:30 PM Daniel Henrique Barboza wrote: > > Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and > made it default for qemu-system-riscv32/64. It was the first RISC-V > machine added in QEMU so setting it as default was sensible. > > Today we have 7 riscv6

Re: [PATCH 07/27] target/riscv: introduce RISCVCPUDef

On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini wrote: > > Start putting all the CPU definitions in a struct. Later this will replace > instance_init functions with declarative code, for now just remove the > ugly cast of class_data. > > Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis

Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target

Hi Alistair, Phil, well, I'm trying to keep the thing alive, checking from time to time that the current QEMU still runs the 128-bit tests that I have, and on which I continue (slowly) to do stuffs. I hope this can stay upstream for experimental/research purposes, but the 128-bit riscv community i

Re: [PATCH 0/2] Add property to support writing ERSTBA in high-low order

Am 6. April 2025 15:30:42 UTC schrieb Guenter Roeck : >On 4/6/25 04:03, Bernhard Beschow wrote: >> >> >> Am 6. April 2025 01:31:49 UTC schrieb Guenter Roeck : >>> On 4/5/25 12:28, Bernhard Beschow wrote: Am 5. April 2025 17:26:14 UTC schrieb Guenter Roeck : > On 4/5/25 07:

Re: [PATCH 0/2] Add property to support writing ERSTBA in high-low order

On 4/6/25 04:03, Bernhard Beschow wrote: Am 6. April 2025 01:31:49 UTC schrieb Guenter Roeck : On 4/5/25 12:28, Bernhard Beschow wrote: Am 5. April 2025 17:26:14 UTC schrieb Guenter Roeck : On 4/5/25 07:25, Philippe Mathieu-Daudé wrote: Hi Guenter, On 5/4/25 16:00, Guenter Roeck wrote:

[PATCH] docs: replace `-hda` with `-drive` & update `root=` kernel parameter

According to QEMU manual: Older options like `-hda` are essentially macros which expand into `-drive` options for various drive interfaces. The original forms bake in a lot of assumptions from the days when QEMU was emulating a legacy PC, they are not recommended for modern configurations. Signed

Re: [PATCH 0/2] Add property to support writing ERSTBA in high-low order

Am 6. April 2025 01:31:49 UTC schrieb Guenter Roeck : >On 4/5/25 12:28, Bernhard Beschow wrote: >> >> >> Am 5. April 2025 17:26:14 UTC schrieb Guenter Roeck : >>> On 4/5/25 07:25, Philippe Mathieu-Daudé wrote: Hi Guenter, On 5/4/25 16:00, Guenter Roeck wrote: > This series

[PATCH 27/27] target/riscv: remove .instance_post_init

Unlike other uses of .instance_post_init, accel_cpu_instance_init() *registers* properties, and therefore must be run before device_post_init() which sets them to their values from -global. In order to move all registration of properties to .instance_init, call accel_cpu_instance_init() at the end

[PATCH 26/27] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 80 +- 1 file changed, 23 insertions(+), 57 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e4d8ddf5a2..0a3a0343087 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 21/27] target/riscv: th: make CSR insertion test a bit more intuitive

In preparation for generalizing the custom CSR functionality, make the test return bool instead of int. Make the insertion_test optional, too. Signed-off-by: Paolo Bonzini --- target/riscv/th_csr.c | 13 - 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target/riscv/th

[PATCH 25/27] target/riscv: convert Ventana V1 to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 75 ++ 1 file changed, 35 insertions(+), 40 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 616d89be17e..4e4d8ddf5a2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 10/27] target/riscv: move RISCVCPUConfig fields to a header file

To support merging a subclass's RISCVCPUDef into the superclass, a list of all the CPU features is needed. Put them into a header file that can be included multiple times, expanding the macros BOOL_FIELD and TYPE_FIELD to different operations. Reviewed-by: Alistair Francis Signed-off-by: Paolo B

[PATCH 13/27] target/riscv: add more RISCVCPUDef fields

Allow using RISCVCPUDef to replicate all the logic of custom .instance_init functions. To simulate inheritance, merge the child's RISCVCPUDef with the parent and then finally move it to the CPUState at the end of TYPE_RISCV_CPU's own instance_init function. Signed-off-by: Paolo Bonzini --- targ

[PATCH 14/27] target/riscv: convert abstract CPU classes to RISCVCPUDef

Start from the top of the hierarchy: dynamic and vendor CPUs are just markers, whereas bare CPUs can have their instance_init function replaced by RISCVCPUDef. The only difference is that the maximum supported SATP mode has to be specified separately for 32-bit and 64-bit modes. Signed-off-by: Pa

[PATCH 02/27] target/riscv: assert argument to set_satp_mode_max_supported is valid

Check that the argument to set_satp_mode_max_supported is valid for the MXL value of the CPU. It would be a bug in the CPU definition if it weren't. In fact, there is such a bug in riscv_bare_cpu_init(): not just SV64 is not a valid VM mode for 32-bit CPUs, SV64 is not a valid VM mode at all, not

[PATCH 22/27] target/riscv: generalize custom CSR functionality

While at it, constify it so that the RISCVCSR array in RISCVCPUDef can also be const. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h| 15 --- target/riscv/cpu.c| 25 - target/riscv/csr.c| 2 +- target/riscv/th_csr.c | 21 +++--

[PATCH 16/27] target/riscv: convert bare CPU models to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 58 ++ 1 file changed, 17 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d3d5c048d02..2ea203d97b7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 20/27] target/riscv: convert SiFive U models to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 79 +++--- 2 files changed, 37 insertions(+), 43 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 0f9be15e47b..1ee05eb393d 100644 --- a/targ

[PATCH 03/27] target/riscv: cpu: store max SATP mode as a single integer

The maximum available SATP mode implies all the shorter virtual address sizes. Store it in RISCVCPUConfig and avoid recomputing it via satp_mode_max_from_map. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 14 ++

[PATCH 09/27] target/riscv: merge riscv_cpu_class_init with the class_base function

Since all TYPE_RISCV_CPU subclasses support a class_data of type RISCVCPUDef, process it even before calling the .class_init function for the subclasses. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 21 ++--- 1 file changed, 10 insertions(+

[PATCH 18/27] target/riscv: convert SiFive E CPU models to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 74 -- 2 files changed, 21 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 4cfdb74891e..0f9be15e47b 100644 --- a/targ

[PATCH 12/27] target/riscv: do not make RISCVCPUConfig fields conditional

Avoid the need for #ifdefs in CPU declarations, keeping them simple. After all class_data used to be specified for all emulators, not just system ones. Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg_fields.h.inc | 2 -- target/riscv/cpu.c| 3 --- 2 files changed, 5 deleti

[PATCH 15/27] target/riscv: convert profile CPU models to RISCVCPUDef

Profile CPUs reuse the instance_init function for bare CPUs; make them proper subclasses instead. Enabling a profile is now done based on the RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef, subclasses check that the parent class's profile is enabled through the parent pr

[PATCH 17/27] target/riscv: convert dynamic CPU models to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 113 - 1 file changed, 30 insertions(+), 83 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2ea203d97b7..73c815d22e9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 24/27] target/riscv: convert TT Ascalon to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 127 + 1 file changed, 60 insertions(+), 67 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 45bed28ea8a..616d89be17e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 06/27] target/riscv: move satp_mode.{map, init} out of CPUConfig

They are used to provide the nice QOM properties for svNN, but the canonical source of the CPU configuration is now cpu->cfg.max_satp_mode. Store them in the ArchCPU struct. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 14 ++ target/riscv/

[PATCH 10.1 v3 00/27] target/riscv: SATP mode and CPU definition overhaul

This is the combination of the previously posted series to store max SATP mode in RISCVCPUConfig as a single integer, and convert CPU definitions to a small extension of RISCVCPUConfig called RISCVCPUDef. I put them together because the first part (patches 1-6) is already acked/reviewed. As menti

[PATCH 11/27] target/riscv: include default value in cpu_cfg_fields.h.inc

In preparation for adding a function to merge two RISCVCPUConfigs (pulling values from the parent if they are not overridden) annotate cpu_cfg_fields.h.inc with the default value of the fields. Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h| 2 +- target/riscv/cpu_cfg_field

[PATCH 23/27] target/riscv: convert TT C906 to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 61 +- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9669e9822b2..45bed28ea8a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH 01/27] hw/riscv: acpi: only create RHCT MMU entry for supported types

Do not create the RHCT MMU type entry for RV32 CPUs, since it only has definitions for SV39/SV48/SV57. Likewise, check that satp_mode_max_from_map() will actually return a valid value, skipping the MMU type entry if all MMU types were disabled on the command line. Acked-by: Alistair Francis Sign

[PATCH 19/27] target/riscv: convert ibex CPU models to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 39 --- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e72ebdf206a..fe1edf3be97 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -691

[PATCH 04/27] target/riscv: update max_satp_mode based on QOM properties

Almost all users of cpu->cfg.satp_mode care about the "max" value satp_mode_max_from_map(cpu->cfg.satp_mode.map). Convert the QOM properties back into it. For TCG, deduce the bitmap of supported modes from valid_vm[]. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv

[PATCH 08/27] target/riscv: store RISCVCPUDef struct directly in the class

Prepare for adding more fields to RISCVCPUDef and reading them in riscv_cpu_init: instead of storing the misa_mxl_max field in RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct and go through it. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.

[PATCH 07/27] target/riscv: introduce RISCVCPUDef

Start putting all the CPU definitions in a struct. Later this will replace instance_init functions with declarative code, for now just remove the ugly cast of class_data. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 4 target/riscv/cpu.c | 27 ++- 2 files

[PATCH 05/27] target/riscv: remove supported from RISCVSATPMap

"supported" can be computed on the fly based on the max_satp_mode. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h | 4 +--- target/riscv/cpu.c | 34 -- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/ta