On Mon, Apr 7, 2025 at 4:24 AM Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr> wrote: > > Hi Alistair, Phil, > well, I'm trying to keep the thing alive, checking from time to time that > the current QEMU still runs the 128-bit tests that I have, and on which > I continue (slowly) to do stuffs.
If it's being used then I don't see any issue keeping it Alistair > I hope this can stay upstream for experimental/research purposes, but the > 128-bit riscv community is, I follow you on that, scarce for now. > > So, your call. > Cheers, > Frédéric > > Le 04/04/2025 à 05:26, Alistair Francis a écrit : > > On Sat, Mar 22, 2025 at 1:09 AM Philippe Mathieu-Daudé > > <phi...@linaro.org> wrote: > >> > >> Hi, > >> > >> On 6/1/22 22:00, Frédéric Pétrot wrote: > >>> This series of patches provides partial 128-bit support for the riscv > >>> target architecture, namely RVI and RVM, with minimal csr support. > >> > >> > >>> Frédéric Pétrot (18): > >>> exec/memop: Adding signedness to quad definitions > >>> exec/memop: Adding signed quad and octo defines > >>> qemu/int128: addition of div/rem 128-bit operations > >>> target/riscv: additional macros to check instruction support > >>> target/riscv: separation of bitwise logic and arithmetic helpers > >>> target/riscv: array for the 64 upper bits of 128-bit registers > >>> target/riscv: setup everything for rv64 to support rv128 execution > >> > >> > >> I see this series has been merged as commit afe33262585, with > >> 332dab68785b describing: > >> > >> This patch adds the support of the '-cpu rv128' option to > >> qemu-system-riscv64 so that we can indicate that we want to > >> run rv128 executables. > >> > >> Still, there is no support for 128-bit insns at that stage > >> so qemu fails miserably (as expected) if launched with this > >> option. > >> > >> Is this code tested? 3 years passed so I wonder about possible > >> code bitrot here. > > > > From memory at the time there was some momentum for RV128. So this was > > merged with the expectation that it would continue to improve. > > > > That doesn't seem to have happened, either software or spec wise though. > > > >> > >> (I reached this code by looking at targets not supporting MTTCG). > > > > I'm happy to remove the CPU if it's blocking you, it's experimental so > > it doesn't need to be deprecated or anything fancy. > > > > Alistair > > > >> > >>> target/riscv: moving some insns close to similar insns > >>> target/riscv: accessors to registers upper part and 128-bit load/store > >>> target/riscv: support for 128-bit bitwise instructions > >>> target/riscv: support for 128-bit U-type instructions > >>> target/riscv: support for 128-bit shift instructions > >>> target/riscv: support for 128-bit arithmetic instructions > >>> target/riscv: support for 128-bit M extension > >>> target/riscv: adding high part of some csrs > >>> target/riscv: helper functions to wrap calls to 128-bit csr insns > >>> target/riscv: modification of the trans_csrxx for 128-bit support > >>> target/riscv: actual functions to realize crs 128-bit insns > >> > >> > > -- > +---------------------------------------------------------------------------+ > | Frédéric Pétrot, Pr. Grenoble INP-UGA@Ensimag/TIMA | > | Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta | > | http://tima.univ-grenoble-alpes.fr frederic.pet...@univ-grenoble-alpes.fr | > +---------------------------------------------------------------------------+ >
