Re: [PATCH 2/6] target/i386: add avx10-version property

On Mon, Oct 28, 2024 at 11:10:45PM +0800, Xiaoyao Li wrote: > On 10/28/2024 10:45 AM, Tao Su wrote: > > Introduce avx10-version property so that avx10 version can be controlled > > by user and cpu model. Per spec, avx10 version can never be 0, the default > > value of avx10-version is set to 0 to d

Re: [PATCH] ui/sdl: Mouse event optimization

> On Fri, 25 Oct 2024, Lei Huang wrote: > > Use a convergence factor to make the VM's input > > global coordinates more closely approach the global > > coordinates of DOM0. > > Dom0 is some Xen terminology. Do you mean "host" which is more often used > in QEMU? Yes, I will change it to host >

Re: [PATCH 3/6] target/i386: Add CPUID.24 leaf for AVX10

On Mon, Oct 28, 2024 at 11:04:07PM +0800, Xiaoyao Li wrote: > On 10/28/2024 10:45 AM, Tao Su wrote: > > +case 0x24: { > > +*eax = 0; > > +*ebx = 0; > > +*ecx = 0; > > +*edx = 0; > > +if (!(env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { > > +

Re: [PATCH 16/21] target/alpha: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the NaN propagation rule explicitly for the float_status word used in this target. This is a no-behaviour-change commit, so we retain the existing behaviour of x87-style pick-largest-significand NaN propagation. This is however not the architecturally

Re: [PATCH 10/21] target/m68k: Initialize float_status fields in gdb set/get functions

On 10/25/24 15:12, Peter Maydell wrote: In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we use a temporary float_status variable to pass to floatx80_to_float64() and float64_to_floatx80(), but we don't initialize it, meaning that those functions could access uninitialized data. Zero-init the st

Re: [PATCH 18/21] target/microblaze: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the NaN propagation rule explicitly for the float_status word used in the microblaze target. This is probably not the architecturally correct behaviour, but since this is a no-behaviour-change patch, we leave a TODO note to that effect. Signed-off-by:

Re: [PATCH 14/21] target/xtensa: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the NaN propagation rule explicitly in xtensa_use_first_nan(). (When we convert the softfloat pickNaNMulAdd routine to also select a NaN propagation rule at runtime, we will be able to remove the use_first_nan flag because the propagation rules will ha

Re: [PATCH 17/21] target/microblaze: Move setting of float rounding mode to reset

On 10/25/24 15:12, Peter Maydell wrote: Although the floating point rounding mode for Microblaze is always nearest-even, we cannot set it just once in the CPU initfn. This is because env->fp_status is in the part of the CPU state struct that is zeroed on reset. Move the call to set_float_roundi

Re: [PATCH 13/21] target/xtensa: Factor out calls to set_use_first_nan()

On 10/25/24 15:12, Peter Maydell wrote: In xtensa we currently call set_use_first_nan() in a lot of places where we want to switch the NaN-propagation handling. We're about to change the softfloat API we use to do that, so start by factoring all the calls out into a single xtensa_use_first_nan()

Re: [PATCH 06/21] target/hppa: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the 2-NaN propagation rule explicitly in env->fp_status. Really we only need to do this at CPU reset (after reset has zeroed out most of the CPU state struct, which typically includes fp_status fields). However target/hppa does not currently implement

Re: [PATCH 05/21] target/loongarch: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the 2-NaN propagation rule explicitly in the float_status word we use. (There are a couple of places in fpu_helper.c where we create a dummy float_status word with "float_status *s = { };", but these are only used for calling float*_is_quiet_nan() so i

Re: [PATCH 09/21] target/m68k: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Explicitly set the 2-NaN propagation rule on env->fp_status and on the temporary fp_status that we use in frem (since we pass that to a division operation function). --- target/m68k/cpu.c | 16 target/m68k/fpu_helper.c

Re: [PATCH 11/21] target/sparc: Move cpu_put_fsr(env, 0) call to reset

On 10/25/24 15:12, Peter Maydell wrote: Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which initializes various fields in the CPU struct: * fsr_cexc_ftt * fcc[] * fsr_qne * fsr It also sets the rounding mode in env->fp_status. This is largely pointless, because when we later

Re: [PATCH 21/21] softfloat: Remove fallback rule from pickNaN()

On 10/25/24 15:12, Peter Maydell wrote: Now that all targets have been converted to explicitly set a NaN propagation rule, we can remove the set of target ifdefs (which now list every target) and clean up the references to fallback behaviour for float_2nan_prop_none. The "default" case in the sw

Re: [PATCH 03/21] target/arm: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the 2-NaN propagation rule explicitly in the float_status words we use. We wrap this plus the pre-existing setting of the tininess-before-rounding flag in a new function arm_set_default_fp_behaviours() to avoid repetition, since we have a lot of float_

Re: [PATCH 20/21] target/rx: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the NaN propagation rule explicitly for the float_status word used in the rx target. This not the architecturally correct behaviour, but since this is a no-behaviour-change patch, we leave a TODO note to that effect. Signed-off-by: Peter Maydell ---

Re: [PATCH 12/21] target/sparc: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the NaN propagation rule explicitly in the float_status words we use. Signed-off-by: Peter Maydell --- target/sparc/cpu.c | 8 target/sparc/fop_helper.c | 10 -- fpu/softfloat-specialize.c.inc | 6 ++ 3 file

Re: [PATCH 19/21] target/openrisc: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the NaN propagation rule explicitly for the float_status word used in the openrisc target. Signed-off-by: Peter Maydell --- target/openrisc/cpu.c | 6 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 7 insertions(+), 1 deleti

Re: [PATCH 15/21] target/i386: Set 2-NaN propagation rule explicitly

On 10/25/24 15:12, Peter Maydell wrote: Set the NaN propagation rule explicitly for the float_status words used in the x86 target. This is a no-behaviour-change commit, so we retain the existing behaviour of using the x87-style "prefer QNaN over SNaN, then prefer the NaN with the larger signific

Re: [PATCH 08/21] target/ppc: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the 2-NaN propagation rule explicitly in env->fp_status and env->vec_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- As an aside, it looks a bit suspicious that we set tininess_before_rounding on fp_status but not vec_sta

Re: [PATCH 07/21] target/s390x: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Set the 2-NaN propagation rule explicitly in env->fpu_status. Signed-off-by: Peter Maydell --- target/s390x/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 5 ++--- 2 files changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Richard Hende

Re: [PATCH 02/21] tests/fp: Explicitly set 2-NaN propagation rule

On 10/25/24 15:12, Peter Maydell wrote: Explicitly set a 2-NaN propagation rule in the softfloat tests. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm propagation rule of float_2nan_prop_s_ab. Signed-off-by: Peter Maydell --- tests/fp/fp-bench.c | 2 +

Re: [PATCH] hw/arm: enable at24c with aspeed

On 28/10/24 15:14, Patrick Leis wrote: Enable AT24C with ASPEED in the KConfig because the boards build this device. Maybe explicit the at24c_eeprom_init_rom() call which instanciate TYPE_AT24C_EE. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Patrick Leis --- hw/arm/Kconfig | 1 +

Re: [PATCH v16 00/20] riscv support for control flow integrity extensions

On Wed, Oct 9, 2024 at 8:52 AM Deepak Gupta wrote: > > v16 for riscv zicfilp and zicfiss extensions support in qemu. > > Following change in this version: > cache block operations of clean, flush and inval have store semantics. > These operations on shadow stack must look like regular stores and m

Re: [PATCH v16 13/20] target/riscv: mmu changes for zicfiss shadow stack protection

On Wed, Oct 9, 2024 at 8:54 AM Deepak Gupta wrote: > > zicfiss protects shadow stack using new page table encodings PTE.W=1, > PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not > implemented or if shadow stack are not enabled. > Loads on shadow stack memory are allowed while stores

Re: [PATCH v16 04/20] target/riscv: save and restore elp state on priv transitions

On Wed, Oct 9, 2024 at 8:52 AM Deepak Gupta wrote: > > elp state is recorded in *status on trap entry (less privilege to higher > privilege) and restored in elp from *status on trap exit (higher to less > privilege). > > Additionally this patch introduces a forward cfi helper function to > determi

Re: [PATCH] hw/arm: enable at24c with aspeed

On Mon, 2024-10-28 at 18:14 +, Patrick Leis wrote: > Enable AT24C with ASPEED in the KConfig because the boards build this > device. > > Signed-off-by: Patrick Leis I was wondering how we haven't hit problems before now. Poking around with scripts/minikconf.py for an arm-softmmu build we get

Re: [PATCH 1/4] qom: TYPE_SINGLETON interface

On Fri, Oct 25, 2024 at 06:10:46PM -0400, Peter Xu wrote: > On Fri, Oct 25, 2024 at 05:22:01PM +0100, Daniel P. Berrangé wrote: > > On Fri, Oct 25, 2024 at 12:17:02PM -0400, Peter Xu wrote: > > > On Fri, Oct 25, 2024 at 10:51:21AM +0100, Daniel P. Berrangé wrote: > > > > > diff --git a/qom/qom-qmp-

Re: [PATCH 13/36] next-cube: move ESCC to be QOM child of next-pc device

On 28/10/2024 16:39, Thomas Huth wrote: Am Wed, 23 Oct 2024 09:58:29 +0100 schrieb Mark Cave-Ayland : Since the ESCC is part of the next-pc device, move the ESCC to be a QOM child of the next-pc device. Signed-off-by: Mark Cave-Ayland --- hw/m68k/next-cube.c | 54 ++-

[PATCH] Plumbed previously ununsed defaults_enabled in vl.c, s.t. it provides the status of the '-nodefaults' flag to created machines

From: Patrick Eads Signed-off-by: Patrick Eads --- .gitignore | 2 ++ hw/core/machine.c | 15 +++ hw/m68k/q800.c | 15 --- include/hw/boards.h | 1 + system/vl.c | 2 +- 5 files changed, 27 insertions(+), 8 deletions(-) diff --git a/.gitignore

Re: [PATCH 10/36] next-cube: move SCSI 4020 logic from next-pc device to next-scsi device

On 28/10/2024 16:22, Thomas Huth wrote: Am Wed, 23 Oct 2024 09:58:26 +0100 schrieb Mark Cave-Ayland : The SCSI 4020 logic refers to the offset of the SCSI CSRs within the NeXTCube address space. Due to the previously overlapping memory regions, there were duplicate MMIO accessors in the next.s

Re: [PATCH 09/36] next-cube: move SCSI CSRs from next-pc to the next-scsi device

On 28/10/2024 16:21, Thomas Huth wrote: Am Wed, 23 Oct 2024 09:58:25 +0100 schrieb Mark Cave-Ayland : The SCSI CSRs are located within the SCSI subsystem of the NeXT PC (Peripheral Contoller) which is now modelled as a separate QEMU device. Add a new VMStateDescription for the next-scsi devic

Re: [PATCH 03/36] next-cube: remove overlap between next.dma and next.mmio memory regions

On 27/10/2024 11:24, Thomas Huth wrote: Am Sat, 26 Oct 2024 22:13:25 +0100 schrieb Mark Cave-Ayland : On 26/10/2024 08:56, Thomas Huth wrote: Am Wed, 23 Oct 2024 09:58:19 +0100 schrieb Mark Cave-Ayland : Change the start of the next.mmio memory region so that it follows on directly afte

Re: [PATCH v4 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On Mon, 28 Oct 2024 at 17:06, Akihiko Odaki wrote: > On 2024/10/28 23:13, Phil Dennis-Jordan wrote: > > > > > > On Mon, 28 Oct 2024 at 15:02, Akihiko Odaki > > wrote: > > > > On 2024/10/28 22:31, Phil Dennis-Jordan wrote: > > > > > > > > > On M

Re: [RFC V1 00/14] precreate phase

On Fri, Oct 25, 2024 at 02:43:06PM +0100, Daniel P. Berrangé wrote: > On Fri, Oct 25, 2024 at 09:33:51AM -0400, Steven Sistare wrote: > > On 10/25/2024 4:46 AM, Daniel P. Berrangé wrote: > > > On Thu, Oct 24, 2024 at 05:16:14PM -0400, Steven Sistare wrote: > > > > > > > > Regarding: "what you want

Re: check-function failing on func-arm-arm_aspeed

Hi Peter, On 10/28/24 10:14, Peter Maydell wrote: Trying a "make check-functional" I find that the func-arm-arm_aspeed test seems to hit a timeout: 18/18 qemu:func-thorough+func-arm-thorough+thorough / func-arm-arm_aspeed TIMEOUT600.08s killed by signal 15 SIGTERM This i

Re: [PATCH] MAINTAINERS: Remove myself as reviewer

On 28/10/2024 09:51, David Gibson wrote: I've now well and truly moved on from ppc and qemu maintenance. I'm occupied with other things and am pretty much just ignoring mails on these topics I'm CCed on. Time to remove myself. I'm still listed as a reviewer for Device Tree, I'll keep this for

Re: [PATCH 0/2] MAINTAINERS: Remove myself from ppc subsystems

On 24/10/2024 20:14, Cédric Le Goater wrote: Hello, My experience with PPC has been over for a few years and now, I'm moving away from PowerNV and XIVE. I wish you the best ! Cheers, C. Cédric Le Goater (2): MAINTAINERS: Remove myself from the PowerNV machines MAINTAINERS: Remove mysel

Re: [RFC 21/21] arm/cpu-features: Document custom vcpu model

On Fri, Oct 25, 2024 at 12:17:40PM +0200, Eric Auger wrote: > From: Cornelia Huck > > Add some documentation for the custom model. > > Signed-off-by: Eric Auger > Signed-off-by: Cornelia Huck > --- > docs/system/arm/cpu-features.rst | 55 +++- > 1 file changed, 47

Re: [PATCH v4] scripts/symlink-install-tree.py: Fix MESONINTROSPECT parsing

On 10/18/24 06:08, Peter Maydell wrote: From: Akihiko Odaki The arguments in MESONINTROSPECT are quoted with shlex.quote() so it must be parsed with shlex.split(). Otherwise the script will fail if the build directory has a character like "~" in it. Note: this fix cannot be backported directl

Re: [PATCH 1/2] ui: Allow injection of vnc display name

Hi Daniel and Marc-André - please excuse my delay (I was traveling last week). I see 2 primary takeaways here: 1. Updating the name field from the ServerInit RFB message to be controlled by the 'name' VNC option 2. Updating where we store the display 'name' in memory For 1 - are we amenable

Re: [PATCH v3 7/8] migration: Unexport migration_is_active()

On Mon, Oct 28, 2024 at 07:20:27PM +0200, Avihai Horon wrote: > > On 28/10/2024 18:58, Peter Xu wrote: > > External email: Use caution opening links or attachments > > > > > > On Mon, Oct 28, 2024 at 06:41:42PM +0200, Avihai Horon wrote: > > > On 28/10/2024 17:45, Peter Xu wrote: > > > > Externa

Re: [PATCH v3 0/7] target/i386: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model

On 10/25/24 00:18, Babu Moger wrote: This series adds the support for following features in qemu. 1. RAS feature bits (SUCCOR, McaOverflowRecov) 2. perfmon-v2 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits 4. Support for bits related to SRSO (sbpb, ibpb-brtype, srso-user-kernel-no) 5. A

Re: [PATCH v2] i386/cpu: Drop the check of phys_bits in host_cpu_realizefn()

Queued, thanks. Paolo

Re: [PATCH v3 0/7] target/i386: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model

On 10/28/24 09:25, Paolo Bonzini wrote: > On Mon, Oct 28, 2024 at 3:23 PM Moger, Babu wrote: >> >> Hi Paolo, >> >> On 10/28/24 03:37, Paolo Bonzini wrote: >>> On 10/25/24 00:18, Babu Moger wrote: This series adds the support for following features in qemu. 1. RAS feature bits (SU

[PATCH v2 1/2] target/riscv/kvm: set 'aia_mode' to default in error path

When failing to set the selected AIA mode, 'aia_mode' is left untouched. This means that 'aia_mode' will not reflect the actual AIA mode, retrieved in 'default_aia_mode', This is benign for now, but it will impact QMP query commands that will expose the 'aia_mode' value, retrieving the wrong value

[PATCH v2 2/2] target/riscv/kvm: clarify how 'riscv-aia' default works

We do not have control in the default 'riscv-aia' default value. We can try to set it to a specific value, in this case 'auto', but there's no guarantee that the host will accept it. Couple with this we're always doing a 'qemu_log' to inform whether we're ended up using the host default or if we m

[PATCH v2 0/2] target/riscv/kvm: riscv-aia fixes

Hi, In this second version we removed patches 3 and 4 from v1. The reasoning behind is that the deprecation process is too harsh in comparison with the user benefit from using bools instead of strings. We'll expose the string property as bools when it's time to expose them in QMP and users will k

Re: [PATCH] hw/arm: enable at24c with aspeed

On Mon, Oct 28, 2024 at 11:15 AM Patrick Leis wrote: > Enable AT24C with ASPEED in the KConfig because the boards build this > device. > > Signed-off-by: Patrick Leis > Reviewed-by: Hao Wu > --- > hw/arm/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/arm/Kconfig b/hw/arm/

[PATCH] linux-user: Add missing mmap include

From: Peter Foley error: use of undeclared identifier 'MAP_FIXED_NOREPLACE' Signed-off-by: Patrick Leis Signed-off-by: Peter Foley --- linux-user/user-mmap.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/user-mmap.h b/linux-user/user-mmap.h index b94bcdcf83..de769f9253 1006

[PATCH] hw/arm: enable at24c with aspeed

Enable AT24C with ASPEED in the KConfig because the boards build this device. Signed-off-by: Patrick Leis --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e7fd9338d1..1b25e73578 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -539,6

Re: [PATCH 0/4] target/riscv/kvm: add riscv-aia bool props

Hi, I had a change of heart w.r.t this work. I still believe that the boolean properties are better to deal with since we don't have to deal with string parsing, and that we should avoid creating new string props in the future. But as far as the user API goes it doesn't matter that much. Havin

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

On Mon, Oct 28, 2024 at 04:48:18PM +, Peter Maydell wrote: > On Mon, 28 Oct 2024 at 16:35, Daniel P. Berrangé wrote: > > > > On Mon, Oct 28, 2024 at 04:16:31PM +, Peter Maydell wrote: > > > On Fri, 25 Oct 2024 at 14:24, Daniel P. Berrangé > > > wrote: > > > > On Fri, Oct 25, 2024 at 03:1

Re: [PATCH v3 7/8] migration: Unexport migration_is_active()

On 28/10/2024 18:58, Peter Xu wrote: External email: Use caution opening links or attachments On Mon, Oct 28, 2024 at 06:41:42PM +0200, Avihai Horon wrote: On 28/10/2024 17:45, Peter Xu wrote: External email: Use caution opening links or attachments On Mon, Oct 28, 2024 at 09:43:16AM +020

check-function failing on func-arm-arm_aspeed

Trying a "make check-functional" I find that the func-arm-arm_aspeed test seems to hit a timeout: 18/18 qemu:func-thorough+func-arm-thorough+thorough / func-arm-arm_aspeed TIMEOUT600.08s killed by signal 15 SIGTERM This is with commit cea8ac78545a. Does anybody else see th

[PULL 08/24] rust: add PL011 device model

From: Manos Pitsidianakis This commit adds a re-implementation of hw/char/pl011.c in Rust. How to build: 1. Configure a QEMU build with: --enable-system --target-list=aarch64-softmmu --enable-rust 2. Launching a VM with qemu-system-aarch64 should use the Rust version of the pl011 device

[PULL 00/24] rust, x86, misc patches for 2024-10-28

The following changes since commit e67b7aef7c7f67ecd0282e903e0daff806d5d680: Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging (2024-10-24 11:23:46 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream-v2 for you to fetch

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

On Mon, Oct 28, 2024 at 04:48:18PM +, Peter Maydell wrote: > On Mon, 28 Oct 2024 at 16:35, Daniel P. Berrangé wrote: > > > > On Mon, Oct 28, 2024 at 04:16:31PM +, Peter Maydell wrote: > > > On Fri, 25 Oct 2024 at 14:24, Daniel P. Berrangé > > > wrote: > > > > On Fri, Oct 25, 2024 at 03:1

[PATCH] hw/sd/sdcard: Fix calculation of size when using eMMC boot partitions

The sd_bootpart_offset() function calculates the *runtime* offset which changes as the guest switches between accessing the main user data area and the boot partitions by writing to the EXT_CSD_PART_CONFIG_ACC_MASK bits, so it shouldn't be used to calculate the main user data area size. Instead, s

Re: [PATCH v1 3/4] system/physmem: Largepage punch hole before reset of memory pages

On 26.10.24 01:27, William Roche wrote: On 10/23/24 09:30, David Hildenbrand wrote: On 22.10.24 23:35, “William Roche wrote: From: William Roche When the VM reboots, a memory reset is performed calling qemu_ram_remap() on all hwpoisoned pages. While we take into account the recorded page siz

Re: [PATCH v3 7/8] migration: Unexport migration_is_active()

On Mon, Oct 28, 2024 at 06:41:42PM +0200, Avihai Horon wrote: > > On 28/10/2024 17:45, Peter Xu wrote: > > External email: Use caution opening links or attachments > > > > > > On Mon, Oct 28, 2024 at 09:43:16AM +0200, Avihai Horon wrote: > > > On 25/10/2024 0:30, Peter Xu wrote: > > > > External

[PULL 05/24] scripts: remove erroneous file that breaks git clone on Windows

From: Pierrick Bouvier This file was created by mistake in recent ed7667188 (9p: remove 'proxy' filesystem backend driver). When cloning the repository using native git for windows, we see this: Error: error: invalid path 'scripts/meson-buildoptions.' Error: The process 'C:\Program Files\Git\bin

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

On Mon, Oct 28, 2024 at 04:16:31PM +, Peter Maydell wrote: > On Fri, 25 Oct 2024 at 14:24, Daniel P. Berrangé wrote: > > On Fri, Oct 25, 2024 at 03:18:25PM +0200, Eric Auger wrote: > > > On 10/25/24 15:06, Daniel P. Berrangé wrote: > > > > Also, is this naming convention really the same one th

Re: [PATCH v2 1/3] qdev-properties: Accept bool for OnOffAuto

The parent msg was sent off-list orignially, so below is a copy of my feedback to that off-list posting. On Tue, Oct 22, 2024 at 01:50:38PM +0900, Akihiko Odaki wrote: > Accept bool literals for OnOffAuto properties for consistency with bool > properties. This enables users to set the "on" or "off

Re: [PATCH v2 2/3] qdev-properties: Add DEFINE_PROP_ON_OFF_AUTO_BIT64()

On Tue, Oct 22, 2024 at 01:50:39PM +0900, Akihiko Odaki wrote: > DEFINE_PROP_ON_OFF_AUTO_BIT64() corresponds to DEFINE_PROP_ON_OFF_AUTO() > as DEFINE_PROP_BIT64() corresponds to DEFINE_PROP_BOOL(). The difference > is that DEFINE_PROP_ON_OFF_AUTO_BIT64() exposes OnOffAuto instead of > bool. Again,

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

On Mon, 28 Oct 2024 at 16:35, Daniel P. Berrangé wrote: > > On Mon, Oct 28, 2024 at 04:16:31PM +, Peter Maydell wrote: > > On Fri, 25 Oct 2024 at 14:24, Daniel P. Berrangé > > wrote: > > > On Fri, Oct 25, 2024 at 03:18:25PM +0200, Eric Auger wrote: > > > > On 10/25/24 15:06, Daniel P. Berran

Re: [RFC 00/21] kvm/arm: Introduce a customizable aarch64 KVM host model

On Mon, 28 Oct 2024 at 16:20, Cornelia Huck wrote: > On Fri, Oct 25 2024, Kashyap Chamarthy wrote: > > (b) The current CPU features doc[2] for Arm doesn't mention "host > > passthrough" at all. It is only implied by the last part of this > > paragraph, from the section titled "A note abo

Re: [PATCH v1 2/4] accel/kvm: Keep track of the HWPoisonPage page_size

On 26.10.24 01:27, William Roche wrote: On 10/23/24 09:28, David Hildenbrand wrote: On 22.10.24 23:35, “William Roche wrote: From: William Roche Add the page size information to the hwpoison_page_list elements. As the kernel doesn't always report the actual poisoned page size, we adjust this

Re: [PATCH v3 7/8] migration: Unexport migration_is_active()

On 28/10/2024 17:45, Peter Xu wrote: External email: Use caution opening links or attachments On Mon, Oct 28, 2024 at 09:43:16AM +0200, Avihai Horon wrote: On 25/10/2024 0:30, Peter Xu wrote: External email: Use caution opening links or attachments We have two outside users of this API, s

Re: [PATCH 13/36] next-cube: move ESCC to be QOM child of next-pc device

Am Wed, 23 Oct 2024 09:58:29 +0100 schrieb Mark Cave-Ayland : > Since the ESCC is part of the next-pc device, move the ESCC to be a QOM child > of the next-pc device. > > Signed-off-by: Mark Cave-Ayland > --- > hw/m68k/next-cube.c | 54 ++--- > 1 file cha

Re: [PATCH 12/36] next-cube: map ESCC registers as a subregion of the next.scr memory region

Am Wed, 23 Oct 2024 09:58:28 +0100 schrieb Mark Cave-Ayland : > Since the ESCC device exists within the memory range of the next.scr memory > region, map > the ESCC device registers as a subregion of the next.scr memory region > instead of > directly to the system address space. > > Signed-off-

Re: [RFC RESEND 0/6] hugetlbfs largepage RAS project

On 19.09.24 18:52, William Roche wrote: Hello David, Hi William, sorry for not replying earlier, it somehow fell through the cracks as my inbox got flooded :( I hope my last week email answered your interrogations about:     - retrieving the valid data from the lost hugepage     - the

Re: [PATCH 10/36] next-cube: move SCSI 4020 logic from next-pc device to next-scsi device

Am Wed, 23 Oct 2024 09:58:26 +0100 schrieb Mark Cave-Ayland : > The SCSI 4020 logic refers to the offset of the SCSI CSRs within the NeXTCube > address space. Due to the previously overlapping memory regions, there were > duplicate MMIO accessors in the next.scr memory region for these registers b

Re: [PATCH 11/36] next-cube: move floppy disk MMIO to separate memory region in next-pc

Am Wed, 23 Oct 2024 09:58:27 +0100 schrieb Mark Cave-Ayland : > The dummy floppy disk device is part of the next-pc device, and not related to > the NeXTCube SCRs. > > Signed-off-by: Mark Cave-Ayland > --- > hw/m68k/next-cube.c | 61 - > 1 file change

Re: [RFC 21/21] arm/cpu-features: Document custom vcpu model

On Mon, Oct 28 2024, Daniel P. Berrangé wrote: > On Mon, Oct 28, 2024 at 05:05:44PM +0100, Cornelia Huck wrote: >> On Fri, Oct 25 2024, Daniel P. Berrangé wrote: >> >> > On Fri, Oct 25, 2024 at 03:28:35PM +0200, Eric Auger wrote: >> >> Hi Daniel, >> >> >> >> On 10/25/24 15:13, Daniel P. Berran

Re: [PATCH 4/6] target/i386: Add feature dependencies for AVX10

On 10/28/2024 10:50 PM, Paolo Bonzini wrote: On Mon, Oct 28, 2024 at 3:48 PM Xiaoyao Li wrote: On 10/28/2024 6:45 PM, Paolo Bonzini wrote: On 10/28/24 11:02, Tao Su wrote: On Mon, Oct 28, 2024 at 09:45:39AM +0100, Paolo Bonzini wrote: On 10/28/24 03:45, Tao Su wrote: Since the highest supp

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

On Mon, Oct 28 2024, Peter Maydell wrote: > On Fri, 25 Oct 2024 at 14:24, Daniel P. Berrangé wrote: >> On Fri, Oct 25, 2024 at 03:18:25PM +0200, Eric Auger wrote: >> > On 10/25/24 15:06, Daniel P. Berrangé wrote: >> > > Also, is this naming convention really the same one that users >> > > will s

Re: [PATCH 09/36] next-cube: move SCSI CSRs from next-pc to the next-scsi device

Am Wed, 23 Oct 2024 09:58:25 +0100 schrieb Mark Cave-Ayland : > The SCSI CSRs are located within the SCSI subsystem of the NeXT PC (Peripheral > Contoller) which is now modelled as a separate QEMU device. > > Add a new VMStateDescription for the next-scsi device to enable the SCSI CSRs > to be mi

Re: [RFC 00/21] kvm/arm: Introduce a customizable aarch64 KVM host model

On Fri, Oct 25 2024, Kashyap Chamarthy wrote: > On Fri, Oct 25, 2024 at 12:17:19PM +0200, Eric Auger wrote: > > Hi Eric, > > I'm new to Arm, so please bear with my questions :) > >> This RFC series introduces a KVM host "custom" model. > > (a) On terminology: as we know, in the x86 world, QEMU us

Re: [PATCH net-next v7] ptp: Add support for the AMZNC10C 'vmclock' device

On 28 October 2024 17:12:56 CET, Jakub Kicinski wrote: >On Sat, 19 Oct 2024 18:49:24 +0100 David Woodhouse wrote: >> > Yes please and thank you! We gotta straighten it out before >> > the merge window. >> >> Hm, as I (finally) come to do that, I realise that many of the others >> defined in dr

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

On Fri, 25 Oct 2024 at 14:24, Daniel P. Berrangé wrote: > On Fri, Oct 25, 2024 at 03:18:25PM +0200, Eric Auger wrote: > > On 10/25/24 15:06, Daniel P. Berrangé wrote: > > > Also, is this naming convention really the same one that users > > > will see when they look at /proc/cpuinfo to view feature

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

On Mon, Oct 28, 2024 at 05:00:46PM +0100, Cornelia Huck wrote: > On Fri, Oct 25 2024, Daniel P. Berrangé wrote: > > > On Fri, Oct 25, 2024 at 03:18:25PM +0200, Eric Auger wrote: > >> Hi Daniel, > >> > >> On 10/25/24 15:06, Daniel P. Berrangé wrote: > >> > On Fri, Oct 25, 2024 at 12:17:37PM +0200

Re: [PATCH net-next v7] ptp: Add support for the AMZNC10C 'vmclock' device

On Sat, 19 Oct 2024 18:49:24 +0100 David Woodhouse wrote: > > Yes please and thank you! We gotta straighten it out before > > the merge window. > > Hm, as I (finally) come to do that, I realise that many of the others > defined in drivers/ptp/Kconfig are also 'default y'. Which is only > really

Re: [PATCH 1/1] target/arm: Add cortex-m0+ support

On Tue, 22 Oct 2024 at 21:34, Matthieu Castet wrote: > > Signed-off-by: Matthieu Castet Hi; thanks for this patch. I have some initial code review comments, but the change looks broadly correct to me and I don't think there's anything obvious missing. The commit message body here is empty. Commi

Re: [RFC 21/21] arm/cpu-features: Document custom vcpu model

On Mon, Oct 28, 2024 at 05:05:44PM +0100, Cornelia Huck wrote: > On Fri, Oct 25 2024, Daniel P. Berrangé wrote: > > > On Fri, Oct 25, 2024 at 03:28:35PM +0200, Eric Auger wrote: > >> Hi Daniel, > >> > >> On 10/25/24 15:13, Daniel P. Berrangé wrote: > >> > On Fri, Oct 25, 2024 at 12:17:40PM +0200

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

On 10/17/2024 5:03 PM, Zhao Liu wrote: On Thu, Oct 17, 2024 at 04:18:06PM +0800, Xiaoyao Li wrote: Date: Thu, 17 Oct 2024 16:18:06 +0800 From: Xiaoyao Li Subject: Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package On 10/14/2024 11:36 AM, Z

Re: [PATCH v4 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On 2024/10/28 23:13, Phil Dennis-Jordan wrote: On Mon, 28 Oct 2024 at 15:02, Akihiko Odaki > wrote: On 2024/10/28 22:31, Phil Dennis-Jordan wrote: > > > On Mon, 28 Oct 2024 at 10:00, Phil Dennis-Jordan mailto:p...@philjordan.eu> > <

[PULL 07/24] Revert "rust: add PL011 device model"

From: Manos Pitsidianakis Patch was applied with invalid authorship by accident, which confuses git tooling that look at git blame for contributors etc. Patch will be re-applied with correct authorship right after this commit. This reverts commit d0f0cd5b1f7e9780753344548e17ad4df9fcf5d8. Signe

Re: [RFC 21/21] arm/cpu-features: Document custom vcpu model

On Fri, Oct 25 2024, Daniel P. Berrangé wrote: > On Fri, Oct 25, 2024 at 03:28:35PM +0200, Eric Auger wrote: >> Hi Daniel, >> >> On 10/25/24 15:13, Daniel P. Berrangé wrote: >> > On Fri, Oct 25, 2024 at 12:17:40PM +0200, Eric Auger wrote: >> >> From: Cornelia Huck >> >> >> >> Add some documenta

Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model

On Fri, Oct 25 2024, Daniel P. Berrangé wrote: > On Fri, Oct 25, 2024 at 03:18:25PM +0200, Eric Auger wrote: >> Hi Daniel, >> >> On 10/25/24 15:06, Daniel P. Berrangé wrote: >> > On Fri, Oct 25, 2024 at 12:17:37PM +0200, Eric Auger wrote: >> >> At the moment, the custom model does not support le

[PATCH 07/14] target/i386: optimize computation of ZF from CC_OP_DYNAMIC

Most uses of CC_OP_DYNAMIC are for CMP/JB/JE or similar sequences. We can optimize many of them to avoid computation of the flags. This eliminates both TCG ops to set up the new cc_op, and helper instructions because evaluating just ZF is much cheaper. Signed-off-by: Paolo Bonzini --- target/i38

Re: [PATCH v3 7/8] migration: Unexport migration_is_active()

On Mon, Oct 28, 2024 at 09:43:16AM +0200, Avihai Horon wrote: > > On 25/10/2024 0:30, Peter Xu wrote: > > External email: Use caution opening links or attachments > > > > > > We have two outside users of this API, so it's exported. > > > > Is it really necessary? Does it matter whether it must

Re: [PATCH v3 8/8] migration: Protect updates to current_migration with a mutex

On Fri, Oct 25, 2024 at 02:50:36PM +0200, Cédric Le Goater wrote: > On 10/24/24 23:30, Peter Xu wrote: > > Introduce migration_mutex, protecting concurrent updates to > > current_migration. > > > > In reality, most of the exported migration functions are safe to access > > migration objects on cap

Re: [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format

On Mon, 28 Oct 2024 at 01:58, Sia Jee Heng wrote: > > Update the SPCR table to accommodate the SPCR Table revision 4 [1]. > The SPCR table has been modified to adhere to the revision 4 format [2]. > > Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to > accommodate the

[PATCH 08/14] target/i386: optimize TEST+Jxx sequences

Mostly used for TEST+JG and TEST+JLE, but it is easy to cover also JBE/JA and JL/JGE; shaves about 0.5% TCG ops. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/target/i386/tc

Re: [PATCH v3 0/7] target/i386: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model

Hi Paolo, On 10/28/24 03:37, Paolo Bonzini wrote: > On 10/25/24 00:18, Babu Moger wrote: >> >> This series adds the support for following features in qemu. >> 1. RAS feature bits (SUCCOR, McaOverflowRecov) >> 2. perfmon-v2 >> 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits >> 4. Support fo

Re: [PATCH 1/1] target/arm: Fix arithmetic underflow in SETM instruction

On Fri, 25 Oct 2024 at 16:50, Michael Tokarev wrote: > > 25.10.2024 05:48, Ido Plat wrote: > > Pass the stage size to step function callback, > > otherwise do_setm would hang when size is larger then page size because > > stage size would underflow. > > This fix changes do_setm to be more inline

Re: [PATCH 3/6] target/i386: Add CPUID.24 leaf for AVX10

On 10/28/2024 10:45 AM, Tao Su wrote: When AVX10 enable bit is set, the 0x24 leaf will be present as "AVX10 Converged Vector ISA leaf" containing fields for the version number and the supported vector bit lengths. Tested-by: Xuelian Guo Signed-off-by: Tao Su --- target/i386/cpu.c | 40 ++

[PATCH 11/14] target/i386: make flag variables unsigned

This makes it easier for the compiler to understand which bits are set, and it also removes "cltq" instructions to canonicalize the output value as 32-bit signed. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/cc_helper_template.h.inc | 46 --

Re: [PATCH v4 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On Mon, 28 Oct 2024 at 10:00, Phil Dennis-Jordan wrote: > > > > >> > > Hmm. I think if we were to use that, we would need to create a >> new >> > > QemuEvent for every job and destroy it afterward, which seems >> > expensive. >> > > We can't rule out multiple concurrent jo

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