Now block-copy will crash if user don't set progress meter by
block_copy_set_progress_meter(). copy-before-write filter will be used
in separate of backup job, and it doesn't want any progress meter (for
now). So, allow not setting it.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/block-
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
qapi/block-core.json | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/qapi/block-core.json b/qapi/block-core.json
index 2ea294129e..f8fbcb6416 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@
We are going to publish copy-before-write filter. So, user should be
able to create it with blockdev-add first, specifying both filtered and
target children. And then do blockdev-reopen, to actually insert the
filter where needed.
Currently, filter unshares write permission unconditionally on sour
No reason to tolerate bdrv_get_info() errors except for ENOTSUP. Let's
just error-out, it's simpler and safer.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/backup.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/block/backup.c b/block/backup.c
index f
Finally, copy-before-write gets own .bdrv_open and .bdrv_close
handlers, block_init() call and becomes available through bdrv_open().
To achieve this:
- cbw_init gets unused flags argument and becomes cbw_open
- block_copy_state_free() call moved to new cbw_close()
- in bdrv_cbw_append:
- o
copy_range is not a default behavior since 6a30f663d4c0b3c, and it's
now available only though x-perf experimantal argument, so it's OK to
drop it.
Even when backup is used to copy disk to same filesystem, and
filesystem supports zero-copy copy_range, copy_range is probably not
what we want for ba
Hi all!
We have image fleecing scheme to export point-in-time state of active
disk (iotest 222):
backup(sync=none)
┌───┐
▼ │
┌┐
Refactor the function to replace child at last. Thus we don't need to
revert it and code is simplified.
block-copy state initilization being done before replacing the child
doesn't need any drained section.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/copy-before-write.c | 33 +
We need an ability to insert filters above top block node, attached to
block device. It can't be achieved with blockdev-reopen command. So, we
want do it with help of qom-set.
Intended usage:
1. blockdev-add, creating the filter, which child is at top node A,
attached to some guest block devic
One more step closer to .bdrv_open(): use options instead of plain
arguments. Move to bdrv_open_child() calls, native for drive open
handlers.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/copy-before-write.c | 37 -
1 file changed, 20 insertions(+), 1
Add field, so property can declare support for setting the property
when device is realized. To be used in the following commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/hw/qdev-properties.h | 1 +
hw/core/qdev-properties.c| 6 +++---
2 files changed, 4 insertions(+), 3 deleti
We are going to convert backup_top to full featured public filter,
which can be used in separate of backup job. Start from renaming from
"how it used" to "what it does".
While updating comments in 283 iotest, drop and rephrase also things
about ".active", as this field is now dropped, and filter d
It won't hurt in common case, so let's not bother with detecting image
fleecing.
Also, we want to simplify initialization interface of copy-before-write
filter as we are going to make it public.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/copy-before-write.h | 2 +-
include/block/bl
On May 12 14:02, Markus Armbruster wrote:
Klaus Jensen writes:
Hi all,
I need some help with grok'ing qdev busses. Stefan, Michael - David
suggested on IRC that I CC'ed you guys since you might have solved a
similar issue with virtio devices. I've tried to study how that works,
but I'm not ex
Add function to change bs inside blk.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/sysemu/block-backend.h | 1 +
block/block-backend.c | 8
2 files changed, 9 insertions(+)
diff --git a/include/sysemu/block-backend.h b/include/sysemu/block-backend.h
index 880e903293
Add function to transactionally replace bs inside BdrvChild.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block.h | 2 ++
block.c | 36
2 files changed, 38 insertions(+)
diff --git a/include/block/block.h b/include/block/block
Now, after huge update of block graph permission update algorithm, we
don't need this workaround with active state of the filter. Drop it and
use new smart bdrv_drop_filter() function.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/copy-on-read.c | 33 +
1
On Sun, May 16, 2021 at 06:28:55PM +0800, Yanan Wang wrote:
> We create and initialize a cpuobj for each present cpu in
> machvirt_init(). Now we also initialize the cpu member of
> structure CPUArchId for each present cpu in the function.
>
> This will be used to determine whether a cpu is presen
On Sun, May 16, 2021 at 06:28:54PM +0800, Yanan Wang wrote:
> From: Andrew Jones
>
> Support device tree CPU topology descriptions.
>
> In accordance with the Devicetree Specification, the Linux Doc
> "arm/cpus.yaml" requires that cpus and cpu nodes in the DT are
> present. And we meet the requi
On Sat, May 15, 2021 at 09:21:48AM +0530, Vaibhav Jain wrote:
> Thanks for looking into this patch David
>
> David Gibson writes:
>
> > On Thu, May 06, 2021 at 08:19:24AM +0530, Vaibhav Jain wrote:
> >> Add support for H_SCM_PERFORMANCE_STATS described at [1] for
> >> spapr nvdimms. This enables
On Sun, May 16, 2021 at 06:28:53PM +0800, Yanan Wang wrote:
> From: Andrew Jones
Hi Yanan,
This looks good, but the authorship is no longer correct. You've
completely rewritten it, so I think the most I deserve is a
Co-developed-by and maybe even just a Suggested-by. When changing
the authorship
On Mon, May 17, 2021 at 12:46:51PM +1000, Nicholas Piggin wrote:
> ISA v3.1 adds new variations of wait, specified by the WC field. These
> are not compatible with the wait 0 implementation, because they add
> additional conditions that cause the processor to resume, which can
> cause software to h
On Sat, May 15, 2021 at 01:07:59PM +0530, Vaibhav Jain wrote:
> Add support for H_SCM_PERFORMANCE_STATS described at [1] for
> spapr nvdimms. This enables guest to fetch performance stats[2] like
> expected life of an nvdimm ('MemLife ') etc and display them to the
> user. Linux kernel support for
On 5/12/21 9:17 AM, Philippe Mathieu-Daudé wrote:
> On 5/6/21 11:33 AM, Philippe Mathieu-Daudé wrote:
>> On 5/6/21 11:10 AM, Philippe Mathieu-Daudé wrote:
>>> On 5/6/21 9:55 AM, Claudio Fontana wrote:
On 5/5/21 9:31 PM, Eduardo Habkost wrote:
> On Wed, May 05, 2021 at 02:15:29PM +0200, Phi
Keep bitmask_transtbl in .rodata by marking the arrays const.
Reviewed-by: Laurent Vivier
Reviewed-by: Richard Henderson
Reviewed-by: Bin Meng
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/syscall.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/sysc
On 4/23/21 3:16 AM, Richard Henderson wrote:
> On 4/22/21 12:38 PM, Philippe Mathieu-Daudé wrote:
>> See rationale in previous commit. Targets should use the vmsd field
>> of DeviceClass, not CPUClass. As migration is not important on the
>> avr/lm32/moxie targets, break the migration compatibility
On 5/17/21 4:49 AM, Bin Meng wrote:
> On Sun, May 16, 2021 at 1:52 AM Philippe Mathieu-Daudé
> wrote:
>>
>> From: Philippe Mathieu-Daudé
>>
>> Looking at the MV64340 model source, there is a dependency on the
>> 8259 interrupt controller:
>>
>> 523 case MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_V
Hi Max,
On Mon, Jan 14, 2019 at 8:52 AM Max Filippov wrote:
>
> Move remaining non-HELPER functions from op_helper.c to helper.c.
> No functional changes.
>
> Signed-off-by: Max Filippov
> ---
> target/xtensa/helper.c| 61
> ---
> target/xtensa/o
On 5/17/21 09:34, BALATON Zoltan wrote:
On Sat, 15 May 2021, BALATON Zoltan wrote:
On Sat, 15 May 2021, BALATON Zoltan wrote:
On Thu, 22 Apr 2021, Alexey Kardashevskiy wrote:
[snip]
+/* Defined as Big Endian */
+struct prom_args {
+ uint32_t service;
+ uint32_t nargs;
+ uint32_t
On 5/16/21 01:04, BALATON Zoltan wrote:
On Thu, 22 Apr 2021, Alexey Kardashevskiy wrote:
[snip]
+/* Defined as Big Endian */
+struct prom_args {
+ uint32_t service;
+ uint32_t nargs;
+ uint32_t nret;
+ uint32_t args[10];
+} QEMU_PACKED;
This #define and struct definition shou
On Fri, May 14, 2021 at 01:22:48PM -0300, Bruno Piazera Larsen wrote:
>
> On 14/05/2021 11:44, Richard Henderson wrote:
> > On 5/14/21 8:29 AM, Bruno Piazera Larsen wrote:
> > >
> > > On 12/05/2021 15:57, Bruno Piazera Larsen wrote:
> > > > On 12/05/2021 15:33, Richard Henderson wrote:
> > > > >
On Thu, May 13, 2021 at 06:44:01PM -0500, Richard Henderson wrote:
65;6401;1c> On 5/13/21 9:03 AM, Lucas Mateus Martins Araujo e Castro wrote:
> > tlb_set_page is called by many ppc_hash64_handle_mmu_fault,
> > ppc_radix64_handle_mmu_fault and ppc_hash32_handle_mmu_fault, all of
> > which from what
On Thu, May 13, 2021 at 11:03:24AM -0300, Lucas Mateus Martins Araujo e Castro
wrote:
>
> On 12/05/2021 15:34, Richard Henderson wrote:
> > On 5/12/21 9:08 AM, Bruno Larsen (billionai) wrote:
> > > From: "Lucas Mateus Castro (alqotel)"
> > >
> > > Added tlb_set_page and tlb_set_page_with_attrs t
On Thu, May 13, 2021 at 09:56:27AM -0300, Bruno Piazera Larsen wrote:
>
> On 13/05/2021 00:59, David Gibson wrote:
> > On Wed, May 12, 2021 at 11:08:12AM -0300, Bruno Larsen (billionai) wrote:
> > > Created a file with stubs needed to compile disabling TCG.
> > >
> > > We're not sure about keepin
On Fri, May 14, 2021 at 09:44:36AM -0500, Richard Henderson wrote:
> On 5/14/21 8:29 AM, Bruno Piazera Larsen wrote:
> >
> > On 12/05/2021 15:57, Bruno Piazera Larsen wrote:
> > > On 12/05/2021 15:33, Richard Henderson wrote:
> > > > On 5/12/21 9:08 AM, Bruno Larsen (billionai) wrote:
> > > > > di
On 5/16/21 06:19, BALATON Zoltan wrote:
On Thu, 22 Apr 2021, Alexey Kardashevskiy wrote:
The PAPR platform describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
require collaboration between the firmware and the hypervisor.
Sinc
On Sat, May 15, 2021 at 07:37:16PM +0200, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé
>
> While the ATI VGA device isn't a requisite (no crash without it):
>
> $ qemu-system-ppc -M pegasos2
> qemu-system-ppc: standard VGA not available
>
> it is useful to have it with the P
On Sat, May 15, 2021 at 07:37:13PM +0200, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé
>
> Looking at the MV64340 model source, there is a dependency on the
> 8259 interrupt controller:
>
> 523 case MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG:
> 524 /* FIXME:
On Sun, May 16, 2021 at 06:28:53PM +0800, Yanan Wang wrote:
> From: Andrew Jones
>
> qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it
> also adds all missing subnodes from the given path. We'll use it
> in a coming patch where we will add cpu-map to the device tree.
>
> And we al
On Sun, May 16, 2021 at 3:41 AM BALATON Zoltan wrote:
>
> On Sat, 15 May 2021, Philippe Mathieu-Daudé wrote:
> > From: Philippe Mathieu-Daudé
> >
> > While the ATI VGA device isn't a requisite (no crash without it):
> >
> > $ qemu-system-ppc -M pegasos2
> > qemu-system-ppc: standard VGA not ava
virtio ring buffer has lockless ring buffer scheme. When guest vcpu
reads the memory, qemu io thread may is writing the same address.
It requiires atomic operation in qemu side, __builtin_memcpy may
read byte-by-byte.
This patch uses fix this, however it may bring negative performance
effect on sy
On Sun, May 16, 2021 at 1:46 AM Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> When building the Pegasos2 machine stand-alone we get:
>
> $ qemu-system-ppc -M pegasos2 -bios pegasos2.rom
> ERROR:qom/object.c:714:object_new_with_type: assertion failed: (type !=
> NULL)
>
On Sun, May 16, 2021 at 1:43 AM Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> The VT82C686 device model misses various dependencies:
>
> /usr/bin/ld: libcommon.fa.p/hw_isa_vt82c686.c.o: in function
> `vt82c686b_realize':
> hw/isa/vt82c686.c:622: undefined reference to `i
On Sun, May 16, 2021 at 1:52 AM Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> Looking at the MV64340 model source, there is a dependency on the
> 8259 interrupt controller:
>
> 523 case MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG:
> 524 /* FIXME: Should th
ISA v3.1 adds new variations of wait, specified by the WC field. These
are not compatible with the wait 0 implementation, because they add
additional conditions that cause the processor to resume, which can
cause software to hang or run very slowly.
Add the new wait variants with a trivial no-op i
On Sun, May 16, 2021 at 1:37 AM Philippe Mathieu-Daudé
wrote:
>
> Per the kconfig.rst:
>
> A device should be listed [...] ``imply`` if (depending on
> the QEMU command line) the board may or may not be started
> without it.
>
> This is the case with the NVDIMM device (it is certainly possi
On Tue, May 11, 2021 at 6:51 PM Philippe Mathieu-Daudé wrote:
>
> Keep bitmask_transtbl in .rodata by marking the arrays const.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> linux-user/syscall.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng
On Fri, May 14, 2021 at 1:26 AM Philippe Mathieu-Daudé wrote:
>
> Inspired-by: Volker Rümelin
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/input/ps2.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Bin Meng
On Sun, May 16, 2021 at 1:44 AM Philippe Mathieu-Daudé
wrote:
>
> Commit a8fb0a500a6 ("hw/char: Add Microchip PolarFire SoC MMUART
> emulation") added a dependency on the SERIAL model, but forgot to
> add the Kconfig selector.
> Add the dependency to the MCHP_PFSOC_MMUART symbol to fix when
> buil
On Mon, May 17, 2021 at 4:50 AM Philippe Mathieu-Daudé wrote:
>
> Headers should be included from the 'include/' directory,
> not from the root directory.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i386/acpi-common.h | 6 +++---
> include/monitor/monitor.h | 2 +-
> hw/gpio/aspeed_
On Mon, May 17, 2021 at 4:53 AM Philippe Mathieu-Daudé wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
Review
On Sat, 15 May 2021, BALATON Zoltan wrote:
On Sat, 15 May 2021, BALATON Zoltan wrote:
On Thu, 22 Apr 2021, Alexey Kardashevskiy wrote:
The PAPR platform describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
require collaboration be
On Mon, May 17, 2021 at 6:53 AM Philippe Mathieu-Daudé wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 2 ++
>
On Fri, May 14, 2021 at 3:24 PM Bin Meng wrote:
>
> riscv_excp_names[] and riscv_intr_names[] are only referenced by
> target/riscv/cpu.c locally.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> target/riscv/cpu.h | 2 --
> target/riscv/cpu.c | 4 ++--
> 2 files
On Sun, May 16, 2021 at 3:47 AM Philippe Mathieu-Daudé
wrote:
>
> Only the Virt and Spike machines use NUMA. Add a RISCV_NUMA Kconfig
> symbol and only have these machines select it. Adapt the Meson file
> to only built it if required.
>
> Acked-by: Paolo Bonzini
> Reviewed-by: Bin Meng
> Signed
On Sun, May 16, 2021 at 3:44 AM Philippe Mathieu-Daudé
wrote:
>
> Commit a8fb0a500a6 ("hw/char: Add Microchip PolarFire SoC MMUART
> emulation") added a dependency on the SERIAL model, but forgot to
> add the Kconfig selector.
> Add the dependency to the MCHP_PFSOC_MMUART symbol to fix when
> buil
On 5/14/21 6:31 PM, Kevin Wolf wrote:
> The following changes since commit 96662996eda78c48aa4e76d8615c7eb72d80:
>
> Merge remote-tracking branch
> 'remotes/dgilbert/tags/pull-migration-20210513a' into staging (2021-05-14
> 12:03:47 +0100)
>
> are available in the Git repository at:
>
>
On 5/14/21 6:31 PM, Kevin Wolf wrote:
> From: Coiby Xu
>
> This test case has the same tests as tests/virtio-blk-test.c except for
> tests have block_resize. Since the vhost-user-blk export only serves one
> client one time, two exports are started by qemu-storage-daemon for the
> hotplug test.
>
On 5/14/21 2:15 PM, Thomas Huth wrote:
> We are generating a lot of target-specific defines in the *-config-devices.h
> and *-config-target.h files. Using them in common code is wrong and leads
> to very subtle bugs since a "#ifdef CONFIG_SOMETHING" is not working there
> as expected. To avoid thes
Oops this is v1, not v2.
On Sun, May 16, 2021 at 10:53 PM Philippe Mathieu-Daudé wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed
Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7e879fb9ca5..0619b491a42 10
Headers should be included from the 'include/' directory,
not from the root directory.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/acpi-common.h | 6 +++---
include/monitor/monitor.h | 2 +-
hw/gpio/aspeed_gpio.c | 2 +-
hw/intc/ppc-uic.c | 2 +-
4 files changed, 6 insertio
Patchew URL: https://patchew.org/QEMU/20210516195855.28869-1-ag...@csgraf.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210516195855.28869-1-ag...@csgraf.de
Subject: [PATCH v7 00/19] hvf: Implement Apple Silicon
We need to handle PSCI calls. Most of the TCG code works for us,
but we can simplify it to only handle aa64 mode and we need to
handle SUSPEND differently.
This patch takes the TCG code as template and duplicates it in HVF.
To tell the guest that we support PSCI 0.2 now, update the check in
arm_c
With Apple Silicon available to the masses, it's a good time to add support
for driving its virtualization extensions from QEMU.
This patch adds all necessary architecture specific code to get basic VMs
working. It's still pretty raw, but definitely functional.
Known limitations:
- Vtimer ackn
We will need more than a single field for hvf going forward. To keep
the global vcpu struct uncluttered, let's allocate a special hvf vcpu
struct, similar to how hax does it.
Signed-off-by: Alexander Graf
Reviewed-by: Roman Bolshakov
Tested-by: Roman Bolshakov
Reviewed-by: Alex Bennée
---
v4
There is no reason to call the hvf specific hvf_cpu_synchronize_state()
when we can just use the generic cpu_synchronize_state() instead. This
allows us to have less dependency on internal function definitions and
allows us to make hvf_cpu_synchronize_state() static.
Signed-off-by: Alexander Graf
Windows 10 calls an SMCCC call via SMC unconditionally on boot. It lives
in the trusted application call number space, but its purpose is unknown.
In our current SMC implementation, we inject a UDEF for unknown SMC calls,
including this one. However, Windows breaks on boot when we do this. Instead
Windows 10 calls an SMCCC call via SMC unconditionally on boot. It lives
in the trusted application call number space, but its purpose is unknown.
In our current SMC implementation, we inject a UDEF for unknown SMC calls,
including this one. However, Windows breaks on boot when we do this. Instead
Now that we have working system register sync, we push more target CPU
properties into the virtual machine. That might be useful in some
situations, but is not the typical case that users want.
So let's add a -cpu host option that allows them to explicitly pass all
CPU capabilities of their host C
Now that we have all logic in place that we need to handle Hypervisor.framework
on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we
can build it.
Signed-off-by: Alexander Graf
Reviewed-by: Roman Bolshakov
Tested-by: Roman Bolshakov (x86 only)
---
v1 -> v2:
- Fix b
The hooks we have that call us after reset, init and loadvm really all
just want to say "The reference of all register state is in the QEMU
vcpu struct, please push it".
We already have a working pushing mechanism though called cpu->vcpu_dirty,
so we can just reuse that for all of the above, synci
The ARM version of Hypervisor.framework no longer defines these two
types, so let's just revert to standard ones.
Signed-off-by: Alexander Graf
---
accel/hvf/hvf-accel-ops.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-
We can move the definition of hvf_vcpu_exec() into our internal
hvf header, obsoleting the need for hvf-accel-ops.h.
Signed-off-by: Alexander Graf
---
accel/hvf/hvf-accel-ops.c | 2 --
accel/hvf/hvf-accel-ops.h | 17 -
include/sysemu/hvf_int.h | 1 +
target/i386/hvf/hvf.c
From: Peter Collingbourne
Sleep on WFI until the VTIMER is due but allow ourselves to be woken
up on IPI.
In this implementation IPI is blocked on the CPU thread at startup and
pselect() is used to atomically unblock the signal and begin sleeping.
The signal is sent unconditionally so there's no
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch moves a few internal struct an
The hvf_set_phys_mem() function is only called within the same file.
Make it static.
Signed-off-by: Alexander Graf
---
accel/hvf/hvf-accel-ops.c | 2 +-
include/sysemu/hvf_int.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-
The hvf accel synchronize functions are only used as input for local
callback functions, so we can make them static.
Signed-off-by: Alexander Graf
---
accel/hvf/hvf-accel-ops.c | 6 +++---
accel/hvf/hvf-accel-ops.h | 3 ---
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/accel/hvf
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch moves the vCPU thread loop ove
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch moves CPU and memory operation
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch moves assert_hvf_ok() and intr
Until now, Hypervisor.framework has only been available on x86_64 systems.
With Apple Silicon shipping now, it extends its reach to aarch64. To
prepare for support for multiple architectures, let's start moving common
code out into its own accel directory.
This patch splits the vcpu init and destr
Now that Apple Silicon is widely available, people are obviously excited
to try and run virtualized workloads on them, such as Linux and Windows.
This patch set implements a fully functional version to get the ball
going on that. With this applied, I can successfully run both Linux and
Windows as
On Fri, 14 May 2021 at 17:04, Michael S. Tsirkin wrote:
>
> The following changes since commit 609d7596524ab204ccd71ef42c9eee4c7c338ea4:
>
> Update version for v6.0.0 release (2021-04-29 18:05:29 +0100)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/virt/kvm/mst/q
There is only one comparison between nwnames and P9_MAXWELEM required.
Signed-off-by: Christian Schoenebeck
---
hw/9pfs/9p.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c
index 0fa776af09..89aa07db78 100644
--- a/hw/9pfs/9p.c
+++ b/hw/9p
On 5/16/21 4:01 PM, Richard Henderson wrote:
> On 5/15/21 5:42 AM, Philippe Mathieu-Daudé wrote:
>> + qemu_log("0x%08" PRIxPTR ": .quad 0x%0*" TCG_PRIlx
>> "\n",
>> + (uintptr_t)&rx_data_gen_ptr[i],
>> + 2 * sizeof(tcg_target_ulong),
When selecting an ARM target on Debian unstable, we get:
Compiling C++ object libcommon.fa.p/disas_libvixl_vixl_utils.cc.o
FAILED: libcommon.fa.p/disas_libvixl_vixl_utils.cc.o
c++ -Ilibcommon.fa.p -I. -I.. [...] -o
libcommon.fa.p/disas_libvixl_vixl_utils.cc.o -c ../disas/libvixl/vixl/utils.
Hi Greg,
while reviewing the 9p code base for further optimizations, I stumbled over
the 'rename_lock' introduced by 02cb7f3a2 and wondered about what exactly it
shall protect?
As far as I understand it, the original intention at introduction
(aforementioned 02cb7f3a2) was to protect
On 5/16/21 2:46 PM, Thomas Huth wrote:
> On 15/05/2021 20.35, Philippe Mathieu-Daudé wrote:
>> When selecting an ARM target on Debian unstable, we get:
>>
>> Compiling C++ object libcommon.fa.p/disas_libvixl_vixl_utils.cc.o
>> FAILED: libcommon.fa.p/disas_libvixl_vixl_utils.cc.o
>> c++ -Il
On Fri, 14 May 2021 at 13:15, Thomas Huth wrote:
>
> Hi Peter!
>
> The following changes since commit 2d3fc4e2b069494b1e9e2e4a1e3de24cbc036426:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-05-12'
> into staging (2021-05-13 20:13:24 +0100)
>
> are available in the Git re
On Sun, 16 May 2021 at 12:16, Alexander Graf wrote:
>
>
> On 28.01.21 17:55, Peter Maydell wrote:
> > Nicer to follow the KVM approach of only doing this once
> > and caching the results in arm_host_cpu_features, so that
> > for a many-cores VM you don't do it once per core.
>
>
> I tend to disagr
On Sat, 15 May 2021 at 18:13, Richard Henderson
wrote:
>
> On 5/13/21 2:25 PM, Peter Maydell wrote:
> >> -VDOT_scalar 1110 0 . 10 1101 . q:1 index:1 u:1 rm:4 \
> >> - vm=%vm_dp vn=%vn_dp vd=%vd_dp
> >> +VDOT_scalar 1110 0 . 10 1101 . q:1 index:1 u:
On Sat, 15 May 2021 at 20:02, Marc-André Lureau
wrote:
> Otherwise, you should get a warning and doc will be disabled. Mine is less
> ugly than yours, not sure why:
I think that's a sphinx-version dependent thing. I requested that
they improve the support for conf.py raising ConfigError to produc
The QEMU project is currently moving its bug tracking to another system.
For this we need to know how to transfer the bug to the new system if
(if still necessary). For this we're setting the status to "Incomplete"
now.
In the unlikely case that the bug has already been fixed in the latest
upstrea
Fix has been merged:
https://gitlab.com/qemu-project/qemu/-/commit/5b2c8af89b82a671137a
** Changed in: qemu
Status: In Progress => Fix Committed
--
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https://bugs.launchpad.net/bugs/1
On Sun, May 16, 2021 at 8:42 PM Philippe Mathieu-Daudé
wrote:
>
> On 5/16/21 2:50 AM, Bin Meng wrote:
> > On Sun, May 16, 2021 at 1:33 AM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 5/14/21 5:02 AM, Bin Meng wrote:
> >>> On Fri, May 14, 2021 at 12:53 AM Philippe Mathieu-Daudé
> >>> wrote:
> >
From: Philippe Mathieu-Daudé
To better visualize the data dumped at the end of a TB, left-align it
(padding it with 0). Print ".long" instead of ".quad" on 32-bit hosts.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210515104202.241504-1-f4...@amsat.org>
[rth: Split the qemu_log and pri
From: Matheus Ferst
Used in ppc D/DS/X-form load/store implementation.
Signed-off-by: Matheus Ferst
Message-Id: <20210512185441.3619828-24-matheus.fe...@eldorado.org.br>
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/tcg
3:24 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210516
for you to fetch changes up to 6c6a4a76eea900112c343ba4f9c5737e298feddf:
accel/tcg: Align data dumped at end of TB (2021-05-16 09:0
On 21.01.21 08:26, Philippe Mathieu-Daudé wrote:
> Hi Alexander,
>
> On 1/20/21 11:44 PM, Alexander Graf wrote:
>> Until now, Hypervisor.framework has only been available on x86_64 systems.
>> With Apple Silicon shipping now, it extends its reach to aarch64. To
>> prepare for support for multiple
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