Reviewing just the QAPI schema.
Maxim Levitsky writes:
> Next few patches will expose that functionality
> to the user.
>
> Signed-off-by: Maxim Levitsky
> ---
> crypto/block-luks.c | 374 +++-
> qapi/crypto.json| 50 +-
> 2 files changed, 421 i
On Tue, 21 Jan 2020 14:41:26 +1100
David Gibson wrote:
> On Wed, Jan 15, 2020 at 07:10:47PM +0100, Cédric Le Goater wrote:
> > On 1/15/20 6:48 PM, Greg Kurz wrote:
> > > Migration can potentially race with CAS reboot. If the migration thread
> > > completes migration after CAS has set spapr->cas_
Philippe Mathieu-Daudé writes:
> Hi Julia,
>
> Cc'ing Markus for the qdev/qbus analysis.
>
> On 1/15/20 11:40 PM, Julia Suvorova wrote:
>> For bus devices, it is useful to be able to handle the parent device.
>>
>> Signed-off-by: Julia Suvorova
>> ---
>> hw/core/qdev.c |
On 21/01/2020 16:11, David Gibson wrote:
> On Fri, Jan 10, 2020 at 01:09:25PM +1100, Alexey Kardashevskiy wrote:
>> The Petitboot bootloader is way more advanced than SLOF is ever going to
>> be as Petitboot comes with the full-featured Linux kernel with all
>> the drivers, and initramdisk with
On 1/21/20 2:33 AM, Joel Stanley wrote:
> This implements the chip id register in the SCU for the ast2500 and
> ast2600. The first patch is a cleanup to separate out ast2400 and
> ast2500 functionality.
These patches apply cleanly on top of :
[v3,0/5] aspeed: extensions and fixes
On 1/21/20 2:33 AM, Joel Stanley wrote:
> This splits the common write callback into separate ast2400 and ast2500
> implementations. This makes it clearer when implementing differing
> behaviour.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> hw/misc/aspeed_scu.c | 80 +
On 1/21/20 2:33 AM, Joel Stanley wrote:
> This returns a fixed but non-zero value for the chip id.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> hw/misc/aspeed_scu.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc
On 1/21/20 4:41 AM, David Gibson wrote:
> On Wed, Jan 15, 2020 at 07:10:47PM +0100, Cédric Le Goater wrote:
>> On 1/15/20 6:48 PM, Greg Kurz wrote:
>>> Migration can potentially race with CAS reboot. If the migration thread
>>> completes migration after CAS has set spapr->cas_reboot but before the
On Tue, Jan 21, 2020 at 12:51:57AM +0100, Philippe Mathieu-Daudé wrote:
> This test runs U-Boot on the Raspberry Pi 2.
> U-Boot is built by the Debian project, see:
> https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
We already have a u-boot submodule in
> From: "Dr. David Alan Gilbert"
>
> When run with vhost-user options we conect to the QEMU instead
> via a socket. Start this off by creating the socket.
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> +/*
> + * Poison the fuse FD so we spot if we accidentally use it;
> + * DO
John Snow writes:
> On 1/17/20 12:30 PM, Peter Maydell wrote:
>> Currently our manual creation includes some .texi files which
>> are autogenerated from .hx files by running scripts/hxtool.
>> .hx files are a simple format, where where a line is either a
>> directive or literal text to be output:
On Mon, Jan 13, 2020 at 01:37:02PM +0100, Igor Mammedov wrote:
> On Thu, 19 Dec 2019 14:47:58 +0800
> Heyi Guo wrote:
>
> > The sub device "PR0" under PCI0 in ACPI/DSDT does not make any sense,
> > so simply remote it.
> Could you make commit message more concrete so it would say
> why it doesn't
On Mon, Jan 20, 2020 at 08:29:47PM +0100, Philippe Mathieu-Daudé wrote:
> Commit c388f408b5 added the possibility to list the display
> backends using '-display help'. Since the 'none' backend is
> is not implemented as a DisplayChangeListenerOps, it is not
> registered to the dpys[] array with qem
On Mon, Jan 20, 2020 at 09:00:51PM -0800, Cameron Esfahani wrote:
> Patch de3f7de7f4e257ce44cdabb90f5f17ee99624557 was too simplistic in its
> implementation: it didn't account for the ZLIB z_stream mutating with
> each compression. Because of the mutation, simply resetting the output
> buffer's o
With VIRTIO_F_MMIO_MSI feature bit offered, the Message Signal
Interrupts (MSI) is supported as first priority. For any reason it
fails to use MSI, it need use the single dedicated interrupt as before.
For MSI vectors and events mapping relationship, introduce in next patch.
Co-developed-by: Chao
Bit 1 msi_sharing reported in the MsiState register indicates the mapping mode
device uses.
Bit 1 is 0 - device uses MSI non-sharing mode. This indicates vector per event
and
fixed static vectors and events relationship. This fits for devices with a high
interrupt
rate and best performance;
Bit
With VIRTIO_F_MMIO_NOTIFICATION feature bit offered, the notification
mechanism is enhanced. Driver reads QueueNotify register to get
notification structure and calculate notification addresses of
each virtqueue.
Co-developed-by: Chao Peng
Signed-off-by: Chao Peng
Co-developed-by: Liu Jiang
Sig
The current MMIO transport layer uses a single, dedicated interrupt
signal, which brings performance penalty. Add a feature bit (40)
for introducing MSI capability.
Co-developed-by: Chao Peng
Signed-off-by: Chao Peng
Co-developed-by: Liu Jiang
Signed-off-by: Liu Jiang
Co-developed-by: Zha Bin
The current virtio over MMIO has some limitations that impact the performance.
It only supports single legacy, dedicated interrupt and one virtqueue
notification register for all virtqueues which cause performance penalties.
To address such limitations, we proposed to update virtio-mmio spec with
All the queues notifications use the same register on MMIO transport
layer. Add a feature bit (39) for enhancing the notification capability.
The detailed mechanism would be in next patch.
Co-developed-by: Chao Peng
Signed-off-by: Chao Peng
Co-developed-by: Liu Jiang
Signed-off-by: Liu Jiang
C
On 20/01/2020 23.01, Philippe Mathieu-Daudé wrote:
> The Arduino Duemilanove is based on a AVR5 CPU, while the
> Arduino MEGA2560 on a AVR6 CPU.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/qtest/boot-serial-test.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/tests/qtes
On Mon, Jan 20, 2020 at 03:11:42PM +, Peter Maydell wrote:
> The preferred way to test whether a trace event is enabled is to
> use trace_event_get_state_backends(), because this will give the
> correct answer (allowing expensive computations to be skipped)
> whether the trace event is compile-
Paolo Bonzini writes:
> On 13/01/20 15:01, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé writes:
>>
>>> When configured with --without-default-devices and setting
>>> MC146818RTC=n, the build fails:
>>>
>>> LINKx86_64-softmmu/qemu-system-x86_64
>>> /usr/bin/ld: qapi/qapi-commands
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.
This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.
Sig
Stefan Hajnoczi writes:
> On Wed, Jan 15, 2020 at 01:15:17PM +0100, Markus Armbruster wrote:
>> Christophe de Dinechin writes:
>> >> On 15 Jan 2020, at 10:20, Markus Armbruster wrote:
>> * qemuMonitorJSONSetIOThread() uses it to control iothread's properties
>> poll-max-ns, poll-grow, poll-sh
Paolo Bonzini writes:
> On 04/01/20 22:16, Philippe Mathieu-Daudé wrote:
>> 1/ the Radeon chip is soldered on the motherboard,
>>
>> 2/ the default BIOS expects the Radeon chip to be
>> unconditionally present,
>>
>> I insist this patch is incorrect for the particular case of the
>> Fuloong2
On Mon, Jan 20, 2020 at 6:59 PM Ian Jiang wrote:
>
> The origin defination of TW bits in mstatus is not correct.
> This patch fixes the problem.
>
> Signed-off-by: Ian Jiang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_bits.h | 2 +-
> 1 file changed, 1 insertion(+), 1 del
On Fri, Jan 10, 2020 at 01:09:25PM +1100, Alexey Kardashevskiy wrote:
> The Petitboot bootloader is way more advanced than SLOF is ever going to
> be as Petitboot comes with the full-featured Linux kernel with all
> the drivers, and initramdisk with quite user friendly interface.
> The problem with
In my investigation, ZRLE always compresses better than ZLIB so
prioritize ZRLE over ZLIB, even if the client hints that ZLIB is
preferred.
zlib buffer is always reset in zrle_compress_data(), so using offset to
calculate next_out and avail_out is useless.
Signed-off-by: Cameron Esfahani
---
ui
Remove VNC optimization to reencode framebuffer update as raw if it's
smaller than the default encoding. QEMU's implementation was naive and
didn't account for the ZLIB z_stream mutating with each compression. Just
saving and restoring the output buffer offset wasn't sufficient to "rewind"
the pr
Patch de3f7de7f4e257ce44cdabb90f5f17ee99624557 was too simplistic in its
implementation: it didn't account for the ZLIB z_stream mutating with
each compression. Because of the mutation, simply resetting the output
buffer's offset wasn't sufficient to "rewind" the operation. The mutated
z_stream w
On Tue, 21 Jan 2020, at 12:03, Joel Stanley wrote:
> This returns a fixed but non-zero value for the chip id.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Andrew Jeffery
> ---
> hw/misc/aspeed_scu.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/misc/aspeed_scu.
On Tue, 21 Jan 2020, at 12:03, Joel Stanley wrote:
> This splits the common write callback into separate ast2400 and ast2500
> implementations. This makes it clearer when implementing differing
> behaviour.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Andrew Jeffery
On Wed, Jan 08, 2020 at 11:10:11AM -0500, Stefan Berger wrote:
> From: Stefan Berger
>
> Signed-off-by: Stefan Berger
Reviewed-by: David Gibson
> ---
> hw/ppc/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
> index f927ec9c74..b5b3519158 1006
On Fri, Jan 17, 2020 at 05:46:21PM +0400, Marc-André Lureau wrote:
> On Fri, Jan 17, 2020 at 5:41 PM Stefan Berger wrote:
> >
> > On 1/17/20 8:31 AM, Marc-André Lureau wrote:
> > > Hi
> > >
> > > On Wed, Jan 8, 2020 at 8:14 PM Stefan Berger
> > > wrote:
> > >> From: Stefan Berger
> > >>
> > >>
On Wed, Jan 08, 2020 at 11:10:08AM -0500, Stefan Berger wrote:
> From: Stefan Berger
>
> For devices that cannot be statically initialized, implement a
> get_dt_compatible() callback that allows us to ask the device for
> the 'compatible' value.
>
> Signed-off-by: Stefan Berger
Reviewed-by: Da
Hi Julia,
Could you provide some comments or advice?
Thanks,
Heyi
在 2020/1/13 20:37, Igor Mammedov 写道:
On Thu, 19 Dec 2019 14:47:58 +0800
Heyi Guo wrote:
The sub device "PR0" under PCI0 in ACPI/DSDT does not make any sense,
so simply remote it.
Could you make commit message more concrete
On Wed, Jan 15, 2020 at 07:10:47PM +0100, Cédric Le Goater wrote:
> On 1/15/20 6:48 PM, Greg Kurz wrote:
> > Migration can potentially race with CAS reboot. If the migration thread
> > completes migration after CAS has set spapr->cas_reboot but before the
> > mainloop could pick up the reset reques
On Mon, Jan 20, 2020 at 09:04:38AM +0100, Greg Kurz wrote:
> On Fri, 17 Jan 2020 16:44:27 +0100
> Greg Kurz wrote:
>
> > On Fri, 17 Jan 2020 19:16:08 +1000
> > David Gibson wrote:
> >
> > > On Thu, Jan 16, 2020 at 07:29:02PM +0100, Greg Kurz wrote:
> > > > On Thu, 16 Jan 2020 13:14:35 +0100
> >
On Mon, Jan 20, 2020 at 11:49:33AM +0100, Cédric Le Goater wrote:
> Hello,
>
> The Processor Control facility for POWER8 processors and later
> provides a mechanism for the hypervisor to send messages to other
> threads in the system (msgsnd instruction) and cause hypervisor-level
> exceptions.
>
On Mon, Jan 20, 2020 at 05:11:50PM -0300, Fabiano Rosas wrote:
> David Gibson writes:
>
> >> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> >> index 103bfe9dc2..b69f8565aa 100644
> >> --- a/target/ppc/cpu.h
> >> +++ b/target/ppc/cpu.h
> >> @@ -440,6 +440,10 @@ typedef struct ppc_v3_pate_t {
>
On 1/20/20 1:48 AM, Alex Bennée wrote:
>> +default:
>> +sigsegv:
>
> this label looks a little extraneous.
>
> Otherwise:
>
> Reviewed-by: Alex Bennée
>
Look a little further down:
> +default:
> +sigsegv:
> +/* Like force_sig(SIGSEGV). */
> +gen_signal(env, T
On Tue, Jan 21, 2020 at 9:53 AM Philippe Mathieu-Daudé wrote:
>
> Since we enabled parallel TCG code generation for softmmu (see
> commit 3468b59 "tcg: enable multiple TCG contexts in softmmu")
> and its subsequent fix (commit 72649619 "add .min_cpus and
> .default_cpus fields to machine_class"),
This patch is not intended to be merged. It just provides a
temporary benchmark foundation for coneniently A/B comparison
of the subsequent 9p readdir optimization patches:
* hw/9pfs/9p-synth: increase amount of simulated files for
readdir test to 2000 files.
* tests/virtio-9p: measure wall tim
This patch is not intended to be merged. It resembles
an issue (with debug messages) where the splitted
readdir test fails because server is interrupted with
transport error "Failed to decode VirtFS request type 40",
which BTW fails both with the unoptimized and with the
optimized 9p readdir code.
A good 9p client sends T_readdir with "count" parameter that's sufficiently
smaller than client's initially negotiated msize (maximum message size).
We perform a check for that though to avoid the server to be interrupted
with a "Failed to encode VirtFS reply type 41" transport error message by
bad
A client establishes a session by sending a Tversion request along with a
'msize' parameter which client uses to suggest server a maximum message
size ever to be used for communication (for both requests and replies)
between client and server during that session. If client suggests a 'msize'
smalle
The previous, already existing readdir test simply used a 'count'
parameter big enough to retrieve all directory entries with a
single Treaddir request.
In this new 'splitted' readdir test, directory entries are
retrieved, splitted over several Treaddir requests by picking small
'count' parameters
This patch is just a temporary benchmark hack, not intended
to be merged!
9pfs synth driver's readdir() implementation has a severe
n-square performance problem. This patch is a quick and dirty
hack to prevent that performance problem from tainting the
readdir() benchmark results. In its current f
The 9p protocol sends strings in general without null termination
over the wire. However for future use of this functions it is
beneficial for the delivered string to be null terminated though
for being able to use the string with standard C functions which
often rely on strings being null terminat
The first readdir test simply checks the amount of directory
entries returned by 9pfs server, according to the created amount
of virtual files on 9pfs synth driver side. Then the subsequent
readdir test also checks whether all directory entries have the
expected file names (as created on 9pfs synth
Make top half really top half and bottom half really bottom half:
Each T_readdir request handling is hopping between threads (main
I/O thread and background I/O driver threads) several times for
every individual directory entry, which sums up to huge latencies
for handling just a single T_readdir
This will provide the following virtual files by the 9pfs
synth driver:
- /ReadDirDir/ReadDirFile99
- /ReadDirDir/ReadDirFile98
...
- /ReadDirDir/ReadDirFile1
- /ReadDirDir/ReadDirFile0
This virtual directory and its virtual 100 files will be
used by the upcoming 9pfs readdir tests.
Si
This patch is not intended to be merged, it measures
and prints the time the 9p server spends on handling
a T_readdir request. It prints the total time it spent
on handling the request, and also the time it spent
on I/O (fs driver) only.
Signed-off-by: Christian Schoenebeck
---
hw/9pfs/9p.c | 21
As previously mentioned, I was investigating performance issues with 9pfs.
Raw file read/write of 9pfs is actually quite good, provided that client
picked a reasonable high msize (maximum message size). I would recommend
to log a warning on 9p server side if a client attached with a small msize
tha
This returns a fixed but non-zero value for the chip id.
Signed-off-by: Joel Stanley
---
hw/misc/aspeed_scu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 7108cad8c6a7..19d1780a40da 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw
This implements the chip id register in the SCU for the ast2500 and
ast2600. The first patch is a cleanup to separate out ast2400 and
ast2500 functionality.
Joel Stanley (2):
aspeed/scu: Create separate write callbacks
aspeed/scu: Implement chip ID register
hw/misc/aspeed_scu.c | 93
This splits the common write callback into separate ast2400 and ast2500
implementations. This makes it clearer when implementing differing
behaviour.
Signed-off-by: Joel Stanley
---
hw/misc/aspeed_scu.c | 80 +++-
1 file changed, 57 insertions(+), 23 delet
The performance increase is due to the multiple RDMA channels instead of
multiple threads, so we must register RAM blocks for the multiple RDMA channels.
Zhimin Feng
-Original Message-
From: Dr. David Alan Gilbert [mailto:dgilb...@redhat.com]
Sent: Monday, January 20, 2020 5:05 PM
To: f
The function riscv_cpu_fp_enabled() is used for checking whether floating
point support is currently enabled. In fact it checks the FS field in the
mstatus MSR.
target/riscv/cpu_helper.c
76 bool riscv_cpu_fp_enabled(CPURISCVState *env)
77 {
78 if (env->mstatus & MSTATUS_FS) {
79 re
CC qemu-block and block maintainers
On 1/17/20 5:34 AM, David Edmondson wrote:
> In many cases the target of a convert operation is a newly provisioned
> target that the user knows is blank (filled with zeroes). In this
> situation there is no requirement for qemu-img to wastefully zero out
> the
On 1/17/20 12:30 PM, Peter Maydell wrote:
> Currently our manual creation includes some .texi files which
> are autogenerated from .hx files by running scripts/hxtool.
> .hx files are a simple format, where where a line is either a
> directive or literal text to be output:
>
> HXCOMM
> -- comm
This test runs U-Boot on the Raspberry Pi 2.
It is very simple and fast:
$ avocado --show=app,console run -t raspi2 -t u-boot tests/acceptance/
JOB LOG: avocado/job-results/job-2020-01-20T23.40-2424777/job.log
(1/1)
tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi
Avocado tags are handy to automatically select tests matching
the tags. Since this test also runs U-Boot, tag it.
We can run all the tests using U-Boot as once with:
$ avocado --show=app run -t u-boot tests/acceptance/
JOB LOG: avocado/job-results/job-2020-01-21T00.16-ee9344e/job.log
(
This test runs U-Boot on the Raspberry Pi 3.
It is very simple and fast:
$ avocado --show=app,console run -t raspi3 -t u-boot tests/acceptance/
JOB LOG: avocado/job-results/job-2020-01-20T23.40-2424777/job.log
(1/1)
tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_aarch64_r
Since we are going to re-use the code shared between
wait_for_console_pattern() and exec_command_and_wait_for_pattern(),
extract the common part into a local function.
Tested-by: Niek Linnenbank
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qemu/__init__.py | 31 +++
We need a function to interrupt interactive consoles.
Example: Interrupt U-Boot to set different environment values.
Tested-by: Niek Linnenbank
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qemu/__init__.py | 32 +--
1 file changed, 30 insertions(+), 2
Currently the QEMU Python module limits the QEMUMachine class to
use the first serial console.
Some machines/guest might use another console than the first one as
the 'boot console'. For example the Raspberry Pi uses the second
(AUX) console.
To be able to use the Nth console as default, we simpl
Since we enabled parallel TCG code generation for softmmu (see
commit 3468b59 "tcg: enable multiple TCG contexts in softmmu")
and its subsequent fix (commit 72649619 "add .min_cpus and
.default_cpus fields to machine_class"), the raspi machines are
restricted to always use their 4 cores:
See in hw
Following Laurent report:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg639950.html
The SYS_timer is already merged, see:
https://git.qemu.org/?p=qemu.git;a=commit;h=d05be883fc
"hw/timer/bcm2835: Add the BCM2835 SYS_timer"
The first patch should fix Laurent other issue.
Then few python pa
On Mon, Jan 20, 2020 at 11:01 PM Philippe Mathieu-Daudé wrote:
>
> Hi,
>
> This series add the arduino boards, aiming at removing the
> 'sample' board that doesn't follow any specification.
>
> Since v3:
> - Rebased on Michael's v41
> - Drop 'extram' unused field (Igor)
> - Renamed devices AVR ->
On Thu, Jan 9, 2020 at 12:52 PM Richard Henderson
wrote:
>
> Merge into the only caller, but at the same time split
> out tlb_mmu_init to initialize a single tlb entry.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> accel/tcg/cputlb.c | 33 +++
On Sun, Jan 19, 2020 at 11:55 PM wrote:
>
> From: Ian Jiang
>
> There is a mistake in defining CSR operations for pmpcfg registers.
> This patch fixes the bug.
>
> Signed-off-by: Ian Jiang
Looks good! Thanks for the patch.
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c |
On Fri, Jan 17, 2020 at 11:36 PM Ian Jiang wrote:
>
> The following registers are given in QEMU debug trace with "-d cpu" parameter.
> pc 1000
> mhartid
> mstatus
> mip 0x0
> mie
> mideleg
> medeleg
On Thu, Jan 9, 2020 at 12:49 PM Richard Henderson
wrote:
>
> I had a conversation with Alistair Francis at KVM forum about
> being able to represent ASIDs "properly". This lead to the idea
> that target-specific code might be able to cache TLBs outside of
> the "main" NB_MMU_MODES -- possibly tho
On Thu, Jan 9, 2020 at 12:55 PM Richard Henderson
wrote:
>
> Do not call get_clock_realtime() in tlb_mmu_resize_locked,
> but hoist outside of any loop over a set of tlbs. This is
> only two (indirect) callers, tlb_flush_by_mmuidx_async_work
> and tlb_flush_page_locked, so not onerous.
>
> Signed
On Thu, Jan 9, 2020 at 12:57 PM Richard Henderson
wrote:
>
> There's little point in leaving these data structures half initialized,
> and relying on a flush to be done during reset.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> accel/tcg/cputlb.c | 5 ++
On Thu, Jan 9, 2020 at 12:52 PM Richard Henderson
wrote:
>
> We will want to be able to flush a tlb without resizing.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> accel/tcg/cputlb.c | 15 ++-
> 1 file changed, 10 insertions(+), 5 deletions(-
On Thu, Jan 9, 2020 at 12:55 PM Richard Henderson
wrote:
>
> No functional change, but the smaller expressions make
> the code easier to read.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> accel/tcg/cputlb.c | 19 ++-
> 1 file changed, 10
On Sat, Jan 18, 2020 at 8:21 PM Michael Rolnik wrote:
>
> This series of patches adds 8bit AVR cores to QEMU.
> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
> yet.
> However I was able to execute simple code with functions. e.g fibonacci
> calculation.
> This ser
Add some microcontrollers from the megaAVR family (ATmega series):
- middle range: ATmega168 and ATmega328
- high range: ATmega1280 and ATmega2560
For product comparison:
https://www.microchip.com/wwwproducts/ProductCompare/ATmega168P/ATmega328P
https://www.microchip.com/wwwproducts/ProductCo
We have one test so far, and it is very fast:
$ avocado --show=app run -t arch:avr tests/acceptance/
(1/1) tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos: PASS (2.13
s)
RESULTS: PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 |
CANCEL 0
JOB TIME : 2.30 s
Sign
The 'arduino-mega-2560-v3' board fully replace the 'sample'
board.
Signed-off-by: Philippe Mathieu-Daudé
---
!squash?
---
default-configs/avr-softmmu.mak | 1 -
hw/avr/sample.c | 295
tests/qtest/boot-serial-test.c | 1 -
hw/avr/Kconfig
As the path name demonstrates, the FreeRTOS tests target a
board based on a ATMega2560 MCU. We have one, the Arduino
MEGA2560.
Complementary documentation:
https://feilipu.me/2012/01/15/ethermega-arduino-mega-2560-and-freertos/
https://feilipu.me/2015/11/24/arduino_freertos/ (see 'Compatibility')
AVR is the architecture, Atmel the manufacturer.
Suggested-by: Aleksandar Markovic
Signed-off-by: Philippe Mathieu-Daudé
---
!squash
---
include/hw/timer/{avr_timer16.h => atmel_timer16.h} | 10 +-
hw/avr/sample.c | 2 +-
hw/timer/{avr_timer16.c => a
Arduino boards are build with AVR chipsets.
Add some of the popular boards:
- Arduino Duemilanove
- Arduino Uno
- Arduino Mega
For more information:
https://www.arduino.cc/en/Main/Products
https://store.arduino.cc/arduino-genuino/most-popular
Reviewed-by: Igor Mammedov
Signed-off-by: Philip
Signed-off-by: Philippe Mathieu-Daudé
---
hw/avr/Kconfig | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
index 516b89c849..228eae7582 100644
--- a/hw/avr/Kconfig
+++ b/hw/avr/Kconfig
@@ -1,6 +1,9 @@
-config AVR_SAMPLE
+config ATMEL_ATMEGA_MC
The Arduino Duemilanove is based on a AVR5 CPU, while the
Arduino MEGA2560 on a AVR6 CPU.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/boot-serial-test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index e556f09db
AVR is the architecture, Atmel the manufacturer.
Suggested-by: Aleksandar Markovic
Signed-off-by: Philippe Mathieu-Daudé
---
!squash
---
include/hw/char/{avr_usart.h => atmel_usart.h} | 10 +-
hw/avr/sample.c| 2 +-
hw/char/{avr_usart.c => atmel_usart.c}
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/misc/avr_mask.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/misc/avr_mask.h b/include/hw/misc/avr_mask.h
index d3e21972d8..5f95e1081d 100644
--- a/include/hw/misc/avr_mask.h
+++ b/include/hw/misc/avr_mask.h
@@ -26,7 +26,6 @@
This device expose 3 different I/O regions. Name them differently
to have a clearer 'info mtree' output.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/avr_timer16.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c
inde
AVR is the architecture, Atmel the manufacturer.
Suggested-by: Aleksandar Markovic
Signed-off-by: Philippe Mathieu-Daudé
---
!squash
---
include/hw/misc/{avr_mask.h => atmel_power.h} | 10 +-
hw/avr/sample.c | 2 +-
hw/misc/{avr_mask.c => atmel_power.c}
Signed-off-by: Philippe Mathieu-Daudé
---
note to maintainer: squash before merge?
---
tests/acceptance/machine_avr6.py | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/tests/acceptance/machine_avr6.py b/tests/acceptance/machine_avr6.py
index 784c287d0b..611f6a62a4 1006
Signed-off-by: Philippe Mathieu-Daudé
---
hw/avr/Makefile.objs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/avr/Makefile.objs b/hw/avr/Makefile.objs
index 626b7064b3..1eb4b53be6 100644
--- a/hw/avr/Makefile.objs
+++ b/hw/avr/Makefile.objs
@@ -1 +1 @@
-obj-y += sample.o
+
Per the datasheet the USART uses 7 consecutive 8-bit registers.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/avr_usart.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/char/avr_usart.c b/hw/char/avr_usart.c
index cb307fe23d..becdb87847 100644
--- a/hw/char/avr_usart.
Signed-off-by: Philippe Mathieu-Daudé
---
!squash
---
MAINTAINERS | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3fbac64b31..4998fee99a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -489,19 +489,6 @@ F: hw/*/allw
Since commit ba21bde93 we don't need to set the machine type
manually, the one set by the ":avocado: tags=machine" will be used.
Suggested-by: Cleber Rosa
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/machine_avr6.py | 1 -
1 file changed, 1 deletion(-)
diff --git a/tests/acceptan
Hi,
This series add the arduino boards, aiming at removing the
'sample' board that doesn't follow any specification.
Since v3:
- Rebased on Michael's v41
- Drop 'extram' unused field (Igor)
- Renamed devices AVR -> Atmel (Aleksandar)
(I haven't renamed structure names to ease review)
Since v2:
Signed-off-by: Philippe Mathieu-Daudé
---
!squash
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c70d77b1ae..3fbac64b31 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -168,7 +168,6 @@ M: Michael Rolnik
R: Sarah Harris
S: Main
On 1/20/20 10:33 AM, Vladimir Sementsov-Ogievskiy wrote:
20.01.2020 17:20, Max Reitz wrote:
On 19.12.19 11:03, Vladimir Sementsov-Ogievskiy wrote:
Hi!
The main feature here is improvement of _next_dirty_area API, which I'm
going to use then for backup / block-copy.
Looks good to me overall,
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