The function riscv_cpu_fp_enabled() is used for checking whether floating
point support is currently enabled. In fact it checks the FS field in the
mstatus MSR.

target/riscv/cpu_helper.c
 76 bool riscv_cpu_fp_enabled(CPURISCVState *env)
 77 {
 78     if (env->mstatus & MSTATUS_FS) {
 79         return true;
 80     }
 81
 82     return false;
 83 }

This will cause a problem that the SD bit in mstatus is not set to 1 when
FS in mstatus is modified from '00'b to '11'b with write_mstatus().

file target/riscv/csr.c, func write_mstatus():
350     dirty = (riscv_cpu_fp_enabled(env) &&
351              ((mstatus & MSTATUS_FS) == MSTATUS_FS)) |
352             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
353     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
354     env->mstatus = mstatus;

So checking fields D and F in the misa MSR (bit 3 and bit 5) may be an
better way. That is
bool riscv_cpu_fp_enabled(CPURISCVState *env)
    if (env->misa & (MISA_F | MISA_F) {
        return true;
    }
    return false;
}


--
Ian Jiang

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