On 05.03.19 08:14, Thomas Huth wrote:
> There are some fields in our struct LowCore which apparently have
> been copied from a very old version of the Linux kernel. These
> fields are not architected in the "Principles of Operation", and
> only used on these memory locations in Linux kernels older
On 01/03/2019 19.59, Jason J. Herne wrote:
> Add struct for format-0 ccws. Support executing format-0 channel
> programs and waiting for their completion before continuing execution.
> This will be used for real dasd ipl.
>
> Add cu_type() to channel io library. This will be used to query control
Patchew URL:
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel
On 01/03/2019 19.59, Jason J. Herne wrote:
> Introduce inline functions to convert between pointers and unsigned 32-bit
> ints. These are used to hide the ugliness required to avoid compiler
> warnings.
>
> Signed-off-by: Jason J. Herne
> Acked-by: Cornelia Huck
> ---
> pc-bios/s390-ccw/helper
On 05/03/2019 07.54, Markus Armbruster wrote:
> Thomas Huth writes:
>
>> On 25/02/2019 19.37, Markus Armbruster wrote:
[...]
>>> diff --git a/vl.c b/vl.c
>>> index e3fdce410f..6ce3d2d448 100644
>>> --- a/vl.c
>>> +++ b/vl.c
>>> @@ -3990,6 +3990,10 @@ int main(int argc, char **argv, char **envp)
>
There are some fields in our struct LowCore which apparently have
been copied from a very old version of the Linux kernel. These
fields are not architected in the "Principles of Operation", and
only used on these memory locations in Linux kernels older than
2.6.29. Newer Linux kernels moved the ent
From: "Dr. David Alan Gilbert"
Add a qmp command that can trigger guest announcements.
It uses its own announce-timer instance, and parameters
passed to it explicitly in the command.
Like most qmp commands, it's in the main thread/bql, so
there's no racing with any outstanding timer.
Based on
From: "Dr. David Alan Gilbert"
We now expose qemu_announce_self through QMP and HMP. Add a test
with some very basic packet validation (make sure we get a RARP).
Signed-off-by: Vlad Yasevich
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Jason Wang
---
From: "Dr. David Alan Gilbert"
The 'announce timer' will be used by migration, and explicit
requests for qemu to perform network announces.
Based on the work by Germano Veit Michel
and Vlad Yasevich
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Jason
Hi Philippe,
On Tue, Mar 05, 2019 at 12:18:01AM +0100, Philippe Mathieu-Daudé wrote:
> >
> > +enum {
> > +LSI_NOWAIT,
>
> You forgot the comment for NOWAIT.
I thought LSI_NOWAIT is self-explaining, but will add that.
> > int waiting;
>
> When a field is not used by migration, you ca
On 05/03/2019 08.09, Thomas Huth wrote:
> There are some fields in our struct LowCore which apparently have
> been copied from a very old version of the Linux kernel. These
> fields are not architected in the "Principles of Operation", and
> only used on these memory locations in Linux kernels olde
From: Vincenzo Maffione
Improve code reuse by implementing netmap_receive() with a call
to netmap_receive_iov().
Signed-off-by: Vincenzo Maffione
Signed-off-by: Jason Wang
---
net/netmap.c | 50 +++---
1 file changed, 11 insertions(+), 39 deletions(
From: "Dr. David Alan Gilbert"
Switch virtio's self announcement to use the AnnounceTimer.
It keeps it's own AnnounceTimer (per device), and starts running it
using a migration post-load and a virtual clock; that way the
announce happens once the guest is actually running.
The timer uses the migr
From: "Dr. David Alan Gilbert"
Expose the virtio-net self announcement capability and allow
qemu_announce_self() to call it.
These announces are caused by something external (i.e. the
announce-self command); they won't trigger if the migration
counter is triggering announces at the same time.
S
From: "Dr. David Alan Gilbert"
Add an HMP command to trigger self annocements.
Unlike the QMP command (which takes a set of parameters), the HMP
command reuses the set of parameters used for migration.
Signend-off-by: Vladislav Yasevich
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Michae
From: "Dr. David Alan Gilbert"
Add migration parameters that control RARP/GARP announcement timeouts.
Based on earlier patches by myself and
Vladislav Yasevich
Signed-off-by: Dr. David Alan Gilbert
Acked-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Jason Wang
---
From: "Dr. David Alan Gilbert"
Switch the announcements to using the new announce timer.
Move the code that does it to announce.c rather than savevm
because it really has nothing to do with the actual migration.
Migration starts the announce from bh's and so they're all
in the main thread/bql, a
From: Zhang Chen
Fix duplicated code:
https://bugs.launchpad.net/qemu/+bug/1811499
Reviewed-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/colo-compare.c | 8
1 file changed, 8 deletions(-)
diff --git a/net/colo-comp
From: "Dr. David Alan Gilbert"
Some network devices have a capability to do self announcements
(ex: virtio-net). Add infrastructure that would allow devices
to expose this ability.
Signed-off-by: Vladislav Yasevich
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Michael S. Tsirkin
Signed-
From: Vincenzo Maffione
Changes:
- Save CPU cycles by computing the return value while scanning the
input iovec, rather than calling iov_size() at the end.
- Remove check for s->tx != NULL, because it cannot happen.
- Cache ring->tail in a local variable and use it to check for
spac
The following changes since commit b6179aaff961627fcb59d7b234297966b81ac726:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-cocoa-20190304' into
staging (2019-03-04 16:50:41 +)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pu
From: Vincenzo Maffione
This change improves the handling of incomplete multi-slot packets
(e.g. with the NS_MOREFRAG set), by advancing ring->head only on
complete packets. The ring->cur pointer is advanced in any case in
order to acknowledge the kernel and move the wake-up point (thus
avoiding
There are some fields in our struct LowCore which apparently have
been copied from a very old version of the Linux kernel. These
fields are not architected in the "Principles of Operation", and
only used on these memory locations in Linux kernels older than
2.6.29. Newer Linux kernels moved the ent
Thomas Huth writes:
> On 25/02/2019 19.37, Markus Armbruster wrote:
>> The first call of sysbus_get_default() creates the main system bus and
>> stores it in QOM as "/machine/unattached/sysbus". This must not
>> happen before main() creates "/machine", or else container_get() would
>> "helpfully
Philippe Mathieu-Daudé writes:
> On 2/25/19 7:37 PM, Markus Armbruster wrote:
>> See the previous commit for rationale.
>>
>> Signed-off-by: Markus Armbruster
>> ---
>> hw/core/qdev.c | 39 ---
>> include/hw/qdev-core.h | 4
>> include/qom/obje
Samuel Thibault writes:
> This uses iconv to convert glyphs from the specified VGA font encoding to
> unicode, and makes use of cchar_t instead of chtype when using ncursesw,
> which allows to store all wide char as well as the WACS values. The default
> charset is made CP437 since that is the ch
On Tue, Mar 05, 2019 at 02:27:48PM +0800, Yi Sun wrote:
> On 19-03-05 13:36:12, Peter Xu wrote:
> > On Tue, Mar 05, 2019 at 01:15:53PM +0800, Yi Sun wrote:
> >
> > [...]
> >
> > > > > w/o passthr
> > > > > -device intel-iommu \
> > > > > -netdev tap,id=net1,vhost=off|on \
> > > > > -d
On 19-03-05 13:36:12, Peter Xu wrote:
> On Tue, Mar 05, 2019 at 01:15:53PM +0800, Yi Sun wrote:
>
> [...]
>
> > > > w/o passthr
> > > > -device intel-iommu \
> > > > -netdev tap,id=net1,vhost=off|on \
> > > > -device virtio-net-pci,netdev=net1 \
> > >
> > > Virtio devices require exp
On 01/03/2019 19.59, Jason J. Herne wrote:
> Create a new header for basic architecture specific definitions and add a
> mapping of low core memory. This mapping will be used by the real dasd boot
> process.
>
> Signed-off-by: Jason J. Herne
> ---
> pc-bios/s390-ccw/main.c | 2 +
> pc-bio
Hi Gerd, Daniel.
We noticed that if VncSharePolicy was configured with
VNC_SHARE_POLICY_FORCE_SHARED mode and
multiple vnc clients opened vnc connections, some clients could go blank screen
at high probability.
This problem can be reproduced when we regularly reboot suse12sp3 in graphic
mode bo
Patchew URL:
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel
On 01/03/2019 19.59, Jason J. Herne wrote:
> Add proper typedefs to all structs and modify all bit fields to use consistent
> formatting.
>
> Signed-off-by: Jason J. Herne
> Reviewed-by: Collin Walling
> Reviewed-by: Farhan Ali
> ---
> pc-bios/s390-ccw/cio.h | 152
> +
On Mon, Mar 04, 2019 at 03:58:00PM +0100, BALATON Zoltan wrote:
> Hello,
>
> I'm trying to implement hardware cursor for ati-vga before submitting the
> last version of it before the freeze.
Use dpy_cursor_define().
cheers,
Gerd
On Tue, Mar 05, 2019 at 01:15:53PM +0800, Yi Sun wrote:
[...]
> > > w/o passthr
> > > -device intel-iommu \
> > > -netdev tap,id=net1,vhost=off|on \
> > > -device virtio-net-pci,netdev=net1 \
> >
> > Virtio devices require explicit enabling of DMAR:
> >
> > https://wiki.qemu.org/Fea
On 19-03-05 12:48:36, Peter Xu wrote:
> On Tue, Mar 05, 2019 at 11:24:24AM +0800, Yi Sun wrote:
> > On 19-03-05 11:09:34, Peter Xu wrote:
> > > On Tue, Mar 05, 2019 at 10:34:52AM +0800, Yi Sun wrote:
> > > > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > > > 'scalable mode', whi
Prior to f6deb6d9 "virtio-balloon: Remove unnecessary MADV_WILLNEED on
deflate", the balloon device issued an madvise() MADV_WILLNEED on
pages removed from the balloon. That would hint to the host kernel
that the pages were likely to be needed by the guest in the near
future.
It's unclear if this
Commits f6deb6d..ee1cd00 made some reworks to the balloon device to
fix behaviour on systems (both host and guest) which don't have 4kiB
pages. However it introduced a couple of problems, which this series
addresses.
David Gibson (2):
virtio-balloon: Fix possible guest memory corruption with in
This fixes a balloon bug with a nasty consequence - potentially
corrupting guest memory - but which is extremely unlikely to be
triggered in practice.
The balloon always works in 4kiB units, but the host could have a
larger page size on certain platforms. Since ed48c59 "virtio-balloon:
Safely han
The SCC/ESCC will briefly stop asserting an interrupt when the
transmit FIFO is filled.
This code doesn't model the transmit FIFO/shift register so the
pending transmit interrupt is never deasserted which means that an
edge-triggered interrupt controller will never see the low-to-high
transition i
On Mon, Mar 04, 2019 at 09:29:24PM -0500, Michael S. Tsirkin wrote:
> On Tue, Mar 05, 2019 at 11:52:08AM +1100, David Gibson wrote:
> > On Thu, Feb 28, 2019 at 08:36:58AM -0500, Michael S. Tsirkin wrote:
> > > On Thu, Feb 14, 2019 at 03:39:12PM +1100, David Gibson wrote:
> > > > When the balloon is
On Thu, Feb 21, 2019 at 09:32:44AM +0100, Cédric Le Goater wrote:
> On 2/21/19 4:13 AM, David Gibson wrote:
> > On Tue, Feb 19, 2019 at 08:31:25AM +0100, Cédric Le Goater wrote:
> >> On 2/12/19 6:40 AM, David Gibson wrote:
> >>> On Mon, Jan 28, 2019 at 10:46:11AM +0100, Cédric Le Goater wrote:
> >
On Mon, Mar 04, 2019 at 09:13:03PM -0500, Michael S. Tsirkin wrote:
> On Tue, Mar 05, 2019 at 11:53:32AM +1100, David Gibson wrote:
> > On Thu, Feb 28, 2019 at 08:39:21AM -0500, Michael S. Tsirkin wrote:
> > > On Thu, Feb 14, 2019 at 03:39:11PM +1100, David Gibson wrote:
> > > > I posted some RFCs
On Tue, Mar 05, 2019 at 01:21:02PM +1100, Suraj Jitindar Singh wrote:
> If we allocate a hash page table then we know that the guest won't be
> using process tables, so set the partition table entry maintained for
> the guest to zero. If this isn't done, then the guest radix bit will
> remain set i
On Tue, Mar 05, 2019 at 11:24:24AM +0800, Yi Sun wrote:
> On 19-03-05 11:09:34, Peter Xu wrote:
> > On Tue, Mar 05, 2019 at 10:34:52AM +0800, Yi Sun wrote:
> > > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > > 'scalable mode', which enables PASID-granular translations for
> > >
On 2019/2/27 下午9:24, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
Hi,
This is a reworking of a few sets of patches from 2017
that were put together by myself, Germano and Vlad that make
the network announce system more flexible.
Firstly, it's parameterised, so tha
On Thu, Feb 28, 2019 at 04:37:25PM +1100, Alexey Kardashevskiy wrote:
> On 28/02/2019 14:49, David Gibson wrote:
> > On Thu, Feb 28, 2019 at 10:59:56AM +1100, Alexey Kardashevskiy wrote:
> >>
> >>
> >> On 28/02/2019 01:33, Greg Kurz wrote:
> >>> On Wed, 27 Feb 2019 19:51:47 +1100
> >>> Alexey Karda
On 19-03-05 11:09:34, Peter Xu wrote:
> On Tue, Mar 05, 2019 at 10:34:52AM +0800, Yi Sun wrote:
> > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > 'scalable mode', which enables PASID-granular translations for
> > first level, second level, nested and pass-through modes. The
> >
On Tue, Mar 05, 2019 at 11:09:34AM +0800, Peter Xu wrote:
> On Tue, Mar 05, 2019 at 10:34:52AM +0800, Yi Sun wrote:
> > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > 'scalable mode', which enables PASID-granular translations for
> > first level, second level, nested and pass-th
On Tue, Mar 05, 2019 at 10:34:52AM +0800, Yi Sun wrote:
> Intel vt-d rev3.0 [1] introduces a new translation mode called
> 'scalable mode', which enables PASID-granular translations for
> first level, second level, nested and pass-through modes. The
> vt-d scalable mode is the key ingredient to ena
On Tue, Mar 05, 2019 at 10:34:55AM +0800, Yi Sun wrote:
> This patch adds an option to provide flexibility for user to expose
> Scalable Mode to guest. User could expose Scalable Mode to guest by
> the config as below:
>
> "-device intel-iommu,caching-mode=on,scalable-mode=on"
>
> The Linux iommu
On Tue, Mar 05, 2019 at 10:34:53AM +0800, Yi Sun wrote:
> From: "Liu, Yi L"
>
> Intel(R) VT-d 3.0 spec introduces scalable mode address translation to
> replace extended context mode. This patch extends current emulator to
> support Scalable Mode which includes root table, context table and new
>
On Mon, Mar 04, 2019 at 11:46:32AM +, Lilijun (Jerry, Cloud Networking)
wrote:
> Hi all,
>
> I am running my VM using vhost-user NIC with OVS-DPDK. The steps of my
> question is shown as follows:
> 1) In the VM, I add one route entry manually on the vNIC eth0 using
> "route add
From: "Liu, Yi L"
Intel(R) VT-d 3.0 spec introduces scalable mode address translation to
replace extended context mode. This patch extends current emulator to
support Scalable Mode which includes root table, context table and new
pasid table format change. Now intel_iommu emulates both legacy mod
Intel vt-d rev3.0 [1] introduces a new translation mode called
'scalable mode', which enables PASID-granular translations for
first level, second level, nested and pass-through modes. The
vt-d scalable mode is the key ingredient to enable Scalable I/O
Virtualization (Scalable IOV) [2] [3], which al
This patch adds an option to provide flexibility for user to expose
Scalable Mode to guest. User could expose Scalable Mode to guest by
the config as below:
"-device intel-iommu,caching-mode=on,scalable-mode=on"
The Linux iommu driver has supported scalable mode. Please refer below
patch set:
From: "Liu, Yi L"
Per Intel(R) VT-d 3.0, the qi_desc is 256 bits in Scalable
Mode. This patch adds emulation of 256bits qi_desc.
Signed-off-by: Liu, Yi L
[Yi Sun is co-developer to rebase and refine the patch.]
Signed-off-by: Yi Sun
Reviewed-by: Peter Xu
---
RFC v2->v1
- do "(val & VTD_IQ
On Tue, Mar 05, 2019 at 11:52:08AM +1100, David Gibson wrote:
> On Thu, Feb 28, 2019 at 08:36:58AM -0500, Michael S. Tsirkin wrote:
> > On Thu, Feb 14, 2019 at 03:39:12PM +1100, David Gibson wrote:
> > > When the balloon is inflated, we discard memory place in it using
> > > madvise()
> > > with M
On 3/5/19 3:11 AM, Michael S. Tsirkin wrote:
> On Tue, Mar 05, 2019 at 01:53:45AM +0100, Philippe Mathieu-Daudé wrote:
>> Hi Michael,
>>
>> On 1/9/18 3:59 PM, Michael S. Tsirkin wrote:
>>> This device is only used on mips malta, move it to the maintainer
>>> that's actually testing it.
>>
>> Slighl
If we allocate a hash page table then we know that the guest won't be
using process tables, so set the partition table entry maintained for
the guest to zero. If this isn't done, then the guest radix bit will
remain set in the entry. This means that when the guest calls
H_REGISTER_PROCESS_TABLE the
On Tue, Mar 05, 2019 at 11:53:32AM +1100, David Gibson wrote:
> On Thu, Feb 28, 2019 at 08:39:21AM -0500, Michael S. Tsirkin wrote:
> > On Thu, Feb 14, 2019 at 03:39:11PM +1100, David Gibson wrote:
> > > I posted some RFCs for this back in December, but didn't wrap it up in
> > > time for 3.1. Pos
On Tue, Mar 05, 2019 at 01:53:45AM +0100, Philippe Mathieu-Daudé wrote:
> Hi Michael,
>
> On 1/9/18 3:59 PM, Michael S. Tsirkin wrote:
> > This device is only used on mips malta, move it to the maintainer
> > that's actually testing it.
>
> Slighly related to this patch, since I included it while
On Thu, Feb 28, 2019 at 05:11:32PM +1100, Alexey Kardashevskiy wrote:
> On 28/02/2019 14:31, David Gibson wrote:
> > On Wed, Feb 27, 2019 at 07:51:49PM +1100, Alexey Kardashevskiy wrote:
> >> NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory
> >> space and accessible as normal
On Thu, Feb 28, 2019 at 08:39:21AM -0500, Michael S. Tsirkin wrote:
> On Thu, Feb 14, 2019 at 03:39:11PM +1100, David Gibson wrote:
> > I posted some RFCs for this back in December, but didn't wrap it up in
> > time for 3.1. Posting again for inclusion in 4.0.
> >
> > The virtio-balloon devices w
On Thu, Feb 28, 2019 at 08:36:58AM -0500, Michael S. Tsirkin wrote:
> On Thu, Feb 14, 2019 at 03:39:12PM +1100, David Gibson wrote:
> > When the balloon is inflated, we discard memory place in it using madvise()
> > with MADV_DONTNEED. And when we deflate it we use MADV_WILLNEED, which
> > sounds
Hi Michael,
On 1/9/18 3:59 PM, Michael S. Tsirkin wrote:
> This device is only used on mips malta, move it to the maintainer
> that's actually testing it.
Slighly related to this patch, since I included it while working on
Kconfig/MIPS.
I splitted PIIX3/PIIX4 (Actually PIIX3 was mixed with I440FX
On 3/4/19 7:20 PM, Paolo Bonzini wrote:
> %-softmmu.mak only keep boards and optional device
> definitions in Kconfig mode.
>
> Signed-off-by: Paolo Bonzini
> ---
> default-configs/lm32-softmmu.mak | 10 ++
> hw/display/Kconfig | 3 +--
> hw/lm32/Kconfig |
On 3/4/19 7:49 PM, Marcel Apfelbaum wrote:
> Configuring QEMU with:
> ../configure --cc=clang --enable-rdma
>
> Leads to compilation error:
>
> CC migration/rdma.o
> CC migration/block.o
> qemu/migration/rdma.c:3615:58: error: taking address of packed member
> 'rkey' of c
On 3/5/19 12:14 AM, Philippe Mathieu-Daudé wrote:
> On 3/4/19 7:09 PM, Sven Schnelle wrote:
>> This makes the code easier to read - no functional change.
>>
>> Signed-off-by: Sven Schnelle
>> ---
>> hw/scsi/lsi53c895a.c | 27 ---
>> 1 file changed, 16 insertions(+), 11 del
On 3/4/19 7:09 PM, Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle
> ---
> hw/scsi/lsi53c895a.c | 24
> 1 file changed, 4 insertions(+), 20 deletions(-)
>
> diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
> index 25c6926039..6d280f8b77 100644
> --- a/hw/scsi
On 3/4/19 7:09 PM, Sven Schnelle wrote:
> This makes the code easier to read - no functional change.
>
> Signed-off-by: Sven Schnelle
> ---
> hw/scsi/lsi53c895a.c | 42 +++---
> 1 file changed, 23 insertions(+), 19 deletions(-)
>
> diff --git a/hw/scsi/lsi53c
On 3/4/19 7:09 PM, Sven Schnelle wrote:
> This makes the code easier to read - no functional change.
>
> Signed-off-by: Sven Schnelle
> ---
> hw/scsi/lsi53c895a.c | 27 ---
> 1 file changed, 16 insertions(+), 11 deletions(-)
>
> diff --git a/hw/scsi/lsi53c895a.c b/hw/scs
Hi Sven,
On 3/4/19 7:09 PM, Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle
> ---
> hw/scsi/lsi53c895a.c | 24 ++--
> hw/scsi/trace-events | 4 ++--
> 2 files changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
> index
Actually compiled something!
root@slax:/dev/shm/pmon/zloader.2edev# qemu-system-mips64el -M fulong2e -cpu
Loongson-2E -m 1G -bios pmon.bin -nographic
PMON2000 MIPS Initializing. Standby...
ERRORPC= CONFIG=00030932
PRID=6302
DIMM read
read memory type
read number of rows
read blocks
On Mon, 04 Mar 2019 11:30:21 PST (-0800), richard.hender...@linaro.org wrote:
On 3/4/19 4:52 AM, Bastian Koppelmann wrote:
This looks like an unforeseen decodetree problem (CC' Richard). As these 16/32
instructions share the same trans_* function, we emit the same typedef once for
16 bit and onc
From: Aleksandar Markovic
A collection of misc target/mips fixes and improvements for March 2019.
v6->v7:
- added a patch on nanomips instruction pool organization in disas
- added a patch on fixing 128-bit test infrastructure
- added a patch on extending MSA wrappers macro functionality
From: Aleksandar Markovic
Add test utilities for 32-bit tests.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/test_inputs_32.h | 122
tests/tcg/mips/include/test_utils_32.h | 78
2 files changed, 200 insertions(+)
create m
On Mon, Mar 04, 2019 at 10:55:39AM +0100, Paolo Bonzini wrote:
>On 04/03/19 07:51, Wei Yang wrote:
>> flatview_add_to_dispatch() registers page based on the condition of
>> *section*, which may looks like this:
>>
>> |s|PPP|s|
>>
>> where s stands for subpage and P for page.
>>
>> The pr
From: Aleksandar Markovic
Add test utilities for 64-bit tests. Some of MIPS64R6 instructions
require 64-bit inputs to be 32-bit integers sign-extedned to 64 bits,
hence the need for sets of such inputs.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/test_inputs_64.h | 208 ++
On 3/4/19 2:38 PM, Sven Schnelle wrote:
Hi Eric,
On Mon, Mar 04, 2019 at 12:40:50PM -0600, Eric Blake wrote:
On 3/4/19 12:09 PM, Sven Schnelle wrote:
Signed-off-by: Sven Schnelle
The commit header says "what" (good), but the commit body says nothing at
all (generally, it should say "why").
From: Aleksandar Markovic
Add macros that will allow testing cases when one of the source
registers is identical to the destination register.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/wrappers_msa.h | 51 +++
1 file changed, 51 insertions(+)
From: Aleksandar Markovic
Add "static" and "const" modifiers where appropriate, and fix other
minor issues.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/test_inputs.h | 4 ++--
tests/tcg/mips/include/test_utils.h | 15 ---
2 files changed, 10 insertions(+), 9 del
This uses iconv to convert glyphs from the specified VGA font encoding to
unicode, and makes use of cchar_t instead of chtype when using ncursesw,
which allows to store all wide char as well as the WACS values. The default
charset is made CP437 since that is the charset of the hardware default VGA
From: Aleksandar Markovic
Add tests for MIPS64R6 bit count instructions.
Signed-off-by: Aleksandar Markovic
---
.../isa/mips64r6/bit-count/test_mips64r6_clo.c | 144 +
.../isa/mips64r6/bit-count/test_mips64r6_clz.c | 144 +
.../isa/mips64r6/bit-c
From: Aleksandar Markovic
Add wrappers for various MSA integer instructions.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/wrappers_msa.h | 70 +++
1 file changed, 70 insertions(+)
diff --git a/tests/tcg/mips/include/wrappers_msa.h
b/tests/tcg/
Hello,
This adds support for wide output in the curses frontend
Difference with previous version:
- Add more rationale in commit message
- Move charset option to curses-only section.
Samuel Thibault (2):
iconv: detect and make curses depend on it
curses: add option to specify VGA font encodi
From: Aleksandar Markovic
Add tests for MIPS64R6 bit swap instructions.
Signed-off-by: Aleksandar Markovic
---
.../isa/mips64r6/bit-swap/test_mips64r6_bitswap.c | 144 +
.../isa/mips64r6/bit-swap/test_mips64r6_dbitswap.c | 144 +
2 files changed, 288 in
From: Aleksandar Markovic
Add graphical description of nanoMIPS instruction pool organization.
Signed-off-by: Aleksandar Markovic
---
disas/nanomips.cpp | 102 +
1 file changed, 102 insertions(+)
diff --git a/disas/nanomips.cpp b/disas/nanom
From: Aleksandar Markovic
Add wrappers for some MIPS64R6 instructions.
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/wrappers_mips64r6.h | 83 ++
1 file changed, 83 insertions(+)
create mode 100644 tests/tcg/mips/include/wrappers_mips64r6.h
diff --
curses will use it for proper wide output support.
Signed-off-by: Samuel Thibault
---
configure | 40
vl.c | 2 +-
2 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index 540bee19ba..9979ca708d 100755
--- a/configu
From: Aleksandar Markovic
Add tests for MIPS64R6 logic instructions.
Signed-off-by: Aleksandar Markovic
---
.../user/isa/mips64r6/logic/test_mips64r6_and.c| 151 +
.../user/isa/mips64r6/logic/test_mips64r6_nor.c| 151 +
.../user/isa/mips64r6/logi
From: Aleksandar Markovic
Add tests for MIPS64R6 bit swap instructions.
Signed-off-by: Aleksandar Markovic
---
.../user/isa/mips64r6/shift/test_mips64r6_dsllv.c | 151 +
.../user/isa/mips64r6/shift/test_mips64r6_dsrav.c | 151 +
.../user/isa/mips64r6/s
From: Aleksandar Markovic
Add tests for MSA pack instructions. This includes following
instructions:
* PCKEV.B - pack even (bytes)
* PCKEV.H - pack even (halfwords)
* PCKEV.W - pack even (words)
* PCKEV.D - pack even (doublewords)
* PCKOD.B - pack odd (bytes)
* PCKOD.H - pack odd (ha
This makes use of wide curses functions instead of 8bit functions. This
allows to type e.g. accented letters.
Unfortunately, key codes are then returned with values that could be
confused with wide characters by ncurses, so we need to add a maybe_keycode
variable to know whether the returned value
From: Aleksandar Markovic
Add tests for MIPS64R6 integer multiply instructions. MUH and MUHU require
64 bit inputs in the form of 64-bit sign-extended 32-bit inputs.
Signed-off-by: Aleksandar Markovic
---
.../isa/mips64r6/int-multiply/test_mips64r6_dmuh.c | 151 +
.../mips6
From: Aleksandar Markovic
Correct comments to handlers of some DSP instructions.
Signed-off-by: Aleksandar Markovic
---
disas/nanomips.cpp | 285 -
1 file changed, 150 insertions(+), 135 deletions(-)
diff --git a/disas/nanomips.cpp b/disas/n
On 3/4/19 9:18 AM, David Kiarie wrote:
i think it is best put as i've updated.
David Kiarie (1):
update copyright notice
hw/i386/amd_iommu.c | 2 +-
hw/i386/amd_iommu.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
You have now posted two separate threads with identical subj
On 3/4/19 7:13 AM, Mateja Marjanovic wrote:
> +} else if (rt == rd) {
> +TCGv_i64 t0 = tcg_temp_new();
> +TCGv_i64 t1 = tcg_temp_new();
> +uint64_t mask0 = (1ULL << 32) - 1;
> +uint64_t mask1 = mask0 << 32;
> +
> +tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
Hi Peter,
Here's the modified patch. I've changed the comment, I hope now it
makes clear that dispite this patch handles the timer enable bit
(which is required for the interrupt), it only adds the periodic IRQ
feature, and not the full timer functionality.
Otherwise I've modified everything you
Patchew URL:
https://patchew.org/QEMU/20190218182851.19714-1-sv...@stackframe.org/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ==
On 3/4/19 7:13 AM, Mateja Marjanovic wrote:
> +if (rd != rt) {
> +tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
> +}
This condition replicates the one inside tcg_gen_mov_i64.
r~
1 - 100 of 505 matches
Mail list logo
