On Sat, Sep 17, 2016 at 7:59 AM, David Kiarie
wrote:
>
>
> On 16/09/16 21:58, Michael S. Tsirkin wrote:
>
>> On Wed, Aug 31, 2016 at 07:17:42PM +0300, David Kiarie wrote:
>>
> Hi Michael,
>
> +
>> +/* issue a PCIe completion packet for devid */
>> +typedef struct QEMU_PACKED {
>> +uint32_t re
On 16/09/16 21:58, Michael S. Tsirkin wrote:
On Wed, Aug 31, 2016 at 07:17:42PM +0300, David Kiarie wrote:
Hi Michael,
+
+/* issue a PCIe completion packet for devid */
+typedef struct QEMU_PACKED {
+uint32_t reserved_1:16;
+uint32_t devid:16;
+
+#ifdef HOST_WORDS_BIGENDIAN
+uint3
On Fri, 2016-09-16 at 22:53 -0400, G 3 wrote:
> Is there a way to make the VGA driver print information? I tried
> building the debug settings in CodeWarrior but it ends with an error.
> I'm trying to add a feature to the driver that will allow the user to
> add resolutions via the command-li
Is there a way to make the VGA driver print information? I tried
building the debug settings in CodeWarrior but it ends with an error.
I'm trying to add a feature to the driver that will allow the user to
add resolutions via the command-line. With the debug output I can
test this driver out
On 09/16/2016 04:54 PM, Emilio G. Cota wrote:
On Fri, Sep 16, 2016 at 10:46:48 -0700, Richard Henderson wrote:
From: "Emilio G. Cota"
With this microbenchmark we can measure the overhead of emulating atomic
instructions with a configurable degree of contention.
The benchmark spawns $n threads
On 09/16/2016 05:16 PM, Emilio G. Cota wrote:
> +uint64_t *haddr = g2h(addr);
> +o0 = ldq_le_p(haddr + 0);
> +o1 = ldq_le_p(haddr + 1);
> +oldv = int128_make128(o0, o1);
> +
> +success = int128_eq(oldv, cmpv);
> +if (success) {
> +stq_le
On Fri, Sep 16, 2016 at 10:46:52 -0700, Richard Henderson wrote:
(snip)
> +/* Returns 0 on success; 1 otherwise. */
> +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
> + uint64_t new_lo, uint64_t new_hi)
> +{
> +uintptr_t ra = GETPC();
With this microbenchmark we can measure the overhead of emulating atomic
instructions with a configurable degree of contention.
The benchmark spawns $n threads, each performing atomic additions in
a loop for $d seconds.
Each atomic operation is performed on a different cache line
(assuming lines a
On Fri, Sep 16, 2016 at 10:46:48 -0700, Richard Henderson wrote:
> From: "Emilio G. Cota"
>
> With this microbenchmark we can measure the overhead of emulating atomic
> instructions with a configurable degree of contention.
>
> The benchmark spawns $n threads, each performing $o atomic ops (addi
On 09/09/2016 06:03 AM, Lluís Vilanova wrote:
-void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)
{
-AlphaCPU *cpu = alpha_env_get_cpu(env);
-CPUState *cs = CPU(cpu);
+CPUAlphaState *env
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1474063242-27419-1-git-send-email-...@twiddle.net
Subject: [Qemu-devel] [PATCH v18 00/13] AVR target
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --on
Signed-off-by: Richard Henderson
---
target-avr/Makefile.objs| 2 -
target-avr/decode.c | 6 +-
target-avr/translate-inst.c | 198 ++--
target-avr/translate-inst.h | 113 -
target-avr/translate.c | 103 ++
From: Michael Rolnik
Signed-off-by: Michael Rolnik
Message-Id: <1471522070-77598-10-git-send-email-mrol...@gmail.com>
Signed-off-by: Richard Henderson
---
target-avr/Makefile.objs | 1 +
target-avr/decode.c | 691 +++
target-avr/translate.c
From: Michael Rolnik
Signed-off-by: Michael Rolnik
Message-Id: <1471522070-77598-8-git-send-email-mrol...@gmail.com>
Signed-off-by: Richard Henderson
---
target-avr/Makefile.objs|1 +
target-avr/translate-inst.c | 2608 +++
target-avr/translate.h
Signed-off-by: Richard Henderson
---
target-avr/translate-inst.c | 298 ++--
target-avr/translate-inst.h | 194 ++--
target-avr/translate.c | 16 +--
target-avr/translate.h | 11 +-
4 files changed, 257 insertions(+), 262
From: Michael Rolnik
Signed-off-by: Michael Rolnik
Message-Id: <1471522070-77598-7-git-send-email-mrol...@gmail.com>
Signed-off-by: Richard Henderson
---
target-avr/cpu.h | 10 +++
target-avr/helper.c| 216 -
target-avr/helper.h|
Signed-off-by: Richard Henderson
---
target-avr/{decode.c => decode.inc.c} | 0
target-avr/{translate-inst.c => translate-inst.inc.c} | 0
target-avr/translate.c| 4 ++--
3 files changed, 2 insertions(+), 2 deletions(-)
rename target-avr/{decode.c
From: Michael Rolnik
Signed-off-by: Michael Rolnik
Message-Id: <1471522070-77598-9-git-send-email-mrol...@gmail.com>
Signed-off-by: Richard Henderson
---
target-avr/cpugen/CMakeLists.txt | 38 +++
target-avr/cpugen/README.md| 17 ++
target-avr/cpugen/cpu/avr.yaml
From: Michael Rolnik
Signed-off-by: Michael Rolnik
Message-Id: <1471522070-77598-5-git-send-email-mrol...@gmail.com>
Signed-off-by: Richard Henderson
---
target-avr/translate-inst.h | 804
1 file changed, 804 insertions(+)
create mode 100644 target
From: Michael Rolnik
Signed-off-by: Michael Rolnik
Message-Id: <1471522070-77598-3-git-send-email-mrol...@gmail.com>
Signed-off-by: Richard Henderson
---
target-avr/cpu.c | 311 +++
target-avr/cpu.h | 48 +
2 files changed, 359 inser
From: Michael Rolnik
1. basic CPU structure
2. registers
3. no instructions
4. saving sreg, rampD, rampX, rampY, rampD, eind in HW representation
Signed-off-by: Michael Rolnik
Message-Id: <1471522070-77598-2-git-send-email-mrol...@gmail.com>
Signed-off-by: Richard Henderson
---
From: Michael Rolnik
Signed-off-by: Michael Rolnik
Message-Id: <1471522070-77598-4-git-send-email-mrol...@gmail.com>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 1 +
hw/avr/Makefile.objs | 21 ++
hw/avr/sample.c | 111
This is Michael's v17, with some adjustments of my own:
(1) Fix the whitespace errors reported by "git am",
(2) Replace the utf-8 characters with normal ascii,
(3) Ditch the separate compilation of translate.c.
I retained the two separate files that could be regenerated
from the included cpugen p
From: Michael Rolnik
Signed-off-by: Michael Rolnik
Message-Id: <1471522070-77598-6-git-send-email-mrol...@gmail.com>
Signed-off-by: Richard Henderson
---
target-avr/helper.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/target-avr/he
I have spent some time investigating a case where qemu is failing to
register xenstore watches for a PV guest once I enable vfb (and
thereby triggering the creation of a qemu instance).
The qemu logs show something along the lines of:
xen be core: xen be core: xen be: watching backend path
(backen
On Fri, Sep 16, 2016 at 07:50:24PM +0400, Marc-André Lureau wrote:
> Those are unneeded now that CPUState nr_{cores,threads} is always
> initialized.
>
> Signed-off-by: Marc-André Lureau
Reviewed-by: Eduardo Habkost
I will wait for at least an Acked-by from the PPC maintainers
before I merge i
Le 16/09/2016 à 13:14, Aleksandar Markovic a écrit :
> From: Aleksandar Markovic
>
> Without this patch, a number of Mips syscalls will be logged in the following
> way (in this examople, this is an invocation of accept4()):
>
> 86906 Unknown syscall 4334
>
> This patch provides standard Qe
Le 16/09/2016 à 13:14, Aleksandar Markovic a écrit :
> From: Aleksandar Markovic
>
> The function that is changed in this patch is supposed to indicate that
> there was certaing argument rearangement related to 64-bit arguments on
> 32-bit platforms. The background on such rearangements can be
Le 16/09/2016 à 13:14, Aleksandar Markovic a écrit :
> From: Aleksandar Markovic
>
> EDQUOT is defined for Mips platform in Linux kernel in such a way
> that it has different value than on most other platforms. However,
> correspondant TARGET_EDQUOT for Mips is missing in Qemu code. Moreover,
>
On Wed, Aug 31, 2016 at 07:17:39PM +0300, David Kiarie wrote:
> Hi all,
>
> This patchset adds basic AMD IOMMU emulation support to Qemu.
>
> Changes since v16 - this is mainly supposed to come as a ping :-)
>-minor endian-ness fixes
This doesn't build on BE so I dropped this.
> Changes si
On Wed, Aug 31, 2016 at 07:17:42PM +0300, David Kiarie wrote:
> +/* serialize IOMMU command processing */
> +typedef struct QEMU_PACKED {
> +#ifdef HOST_WORDS_BIGENDIAN
> +uint64_t type:4; /* command type */
> +uint64_t reserved:8;
> +uint64_t store_addr:49;
Le 16/09/2016 à 13:14, Aleksandar Markovic a écrit :
> From: Aleksandar Markovic
>
> This patch corrects target_semid64_ds structure definition for Mips.
>
> See, for example definition of semid64_ds for Mips in Linux kernel:
> arch/mips/include/uapi/asm/sembuf.h#L13.
>
> This patch will also
From: Maxime Coquelin
Currently, devices are plugged before features are negotiated.
If the backend doesn't support VIRTIO_F_VERSION_1, the transport
needs to rewind some settings.
This is the case for CCW, for which a post_plugged callback had
been introduced, where max_rev field is just update
From: Greg Kurz
Except virtio-9p, all virtio-* tests are orphan. This patch tries to fix
it, according to the following logic:
- when the related subsystem has its own section in MAINTAINERS, the test
is added there
- otherwise it is added to the "parent" section (aka. SCSI, Network devices,
The following changes since commit d1eb8f2acba579830cf3798c3c15ce51be852c56:
fpu: add mechanism to check for invalid long double formats (2016-09-15
12:43:18 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
for you to fetch
On Fri, Sep 16, 2016 at 11:57:54AM +0100, Peter Maydell wrote:
> On 15 September 2016 at 21:38, Michael S. Tsirkin wrote:
> > The following changes since commit d1eb8f2acba579830cf3798c3c15ce51be852c56:
> >
> > fpu: add mechanism to check for invalid long double formats (2016-09-15
> > 12:43:18
This double free did not cause harm because v9fs_string_free() sets
str->data to NULL and g_free(NULL) is valid.
Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goater
---
hw/9pfs/9p-proxy.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/9pfs/9p-proxy.c b/hw/9pfs/9p-proxy.c
index 52bbf4f
Le 16/09/2016 à 13:14, Aleksandar Markovic a écrit :
> From: Aleksandar Markovic
>
> For some reason, Qemu's TARGET_F_GETOWN constant for Mips does not
> match the correct value of correspondant F_GETOWN. This patch fixes
> this problem.
>
> For reference, see Mips' F_GETOWN definition in Linu
The following changes since commit 5f473241ac595452ae0638dc63e7af2a2294f5ec:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2016-09-15 18:12:40 +0100)
are available in the git repository at:
https://github.com/gkurz/qemu.git tags/for-upstream
for you to fetc
Le 16/09/2016 à 13:14, Aleksandar Markovic a écrit :
> From: Aleksandar Markovic
>
> Structure flock is defined for Mips in a way different from any
> other platform. For reference, see Linux kernel source code files:
>
> arch/mips/include/uapi/asm/fcntl.h, line 63 (for Mips)
> include/uapi/as
If the call to fid_to_qid() returns an error, we will call v9fs_path_free()
on uninitialized paths.
It is a regression introduced by the following commit:
56f101ecce0e 9pfs: handle walk of ".." in the root directory
Let's fix this by initializing dpath and path before calling fid_to_qid().
Sign
Rather than using helpers for physical accesses, use a mmu index.
The primary cleanup is with store-conditional on physical addresses.
Signed-off-by: Richard Henderson
---
target-alpha/cpu.h| 18 +---
target-alpha/helper.c | 8 ++
target-alpha/helper.h | 9 --
t
From: "Emilio G. Cota"
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-25-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-arm/translate.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/target-arm/translate.
This adds a simple test to validate the device is functional: it transmits
a request with type Terror, which is not used by the 9P protocol [1], and
expects QEMU to return a reply with type Rerror and the "Operation not
supported" error string.
[1] http://lxr.free-electrons.com/source/include/net/
This adds PCI init code and a basic test that checks the device config
matches what is passed on the command line.
Signed-off-by: Greg Kurz
Acked-by: Cornelia Huck
---
tests/Makefile.include | 2 +-
tests/virtio-9p-test.c | 77 ++
2 files changed
From: "Emilio G. Cota"
Emulating LL/SC with cmpxchg is not correct, since it can
suffer from the ABA problem. Portable parallel code, however,
is written assuming only cmpxchg--and not LL/SC--is available.
This means that in practice emulating LL/SC with cmpxchg is
a viable alternative.
The appe
First step to be able to run several functional steps.
Signed-off-by: Greg Kurz
Acked-by: Cornelia Huck
---
tests/virtio-9p-test.c | 42 +-
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/tests/virtio-9p-test.c b/tests/virtio-9p-test.c
ind
From: "Emilio G. Cota"
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-19-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/tr
From: "Emilio G. Cota"
[rth: Eliminate some unnecessary temporaries.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-13-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 76 +
1 file chang
From: "Emilio G. Cota"
Emulating LL/SC with cmpxchg is not correct, since it can
suffer from the ABA problem. Portable parallel code, however,
is written assuming only cmpxchg--and not LL/SC--is available.
This means that in practice emulating LL/SC with cmpxchg is
a viable alternative.
The appe
This helper is similar to v9fs_string_sprintf(), but it includes the
terminating NUL character in the size field.
This is to avoid doing v9fs_string_sprintf((V9fsString *) &path) and
then bumping the size.
Affected users are changed to use this new helper.
Signed-off-by: Greg Kurz
Reviewed-by:
From: "Emilio G. Cota"
[rth: Merge gen_inc_locked back into gen_inc to share cc update.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-14-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 24 +---
1 file changed, 13
From: "Emilio G. Cota"
The exception is not emitted anymore; remove it and the associated
TCG variables.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-31-git-send-email-c...@braap.org>
---
target-arm/cpu.h | 17 +++
Le 16/09/2016 à 13:14, Aleksandar Markovic a écrit :
> From: Aleksandar Markovic
>
> This patch fixes wrong definition of TARGET_SIOCATMARK for Mips.
>
> The current definition is:
>
> #define SIOCATMARK 0x8905
>
> while the correct definition is:
>
> #define SIOCATMARK TARGET
The v9fs_string_null() function just calls v9fs_string_free(). Also it
only has 4 users, whereas v9fs_string_free() has 87.
This patch converts users to call directly v9fs_string_free() and drops
the useless function.
Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goater
---
fsdev/9p-marshal.
Force the use of cmpxchg16b on x86_64.
Wikipedia suggests that only very old AMD64 (circa 2004) did not have
this instruction. Further, it's required by Windows 8 so no new cpus
will ever omit it.
If we truely care about these, then we could check this at startup time
and then avoid executing pa
From: "Emilio G. Cota"
The exception is not emitted anymore.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-30-git-send-email-c...@braap.org>
---
linux-user/main.c | 125 ---
Emulating LL/SC with cmpxchg is not correct, since it can
suffer from the ABA problem. However, portable parallel
code is writting assuming only cmpxchg which means that in
practice this is a viable alternative.
Signed-off-by: Richard Henderson
---
linux-user/main.c| 49 ---
Allow qemu to build on 32-bit hosts without 64-bit atomic ops.
Even if we only allow 32-bit hosts to multi-thread emulate 32-bit
guests, we still need some way to handle the 32-bit guest using a
64-bit atomic operation. Do so by dropping back to single-step.
Signed-off-by: Richard Henderson
---
Stop specializing on TARGET_LONG_BITS == 32; unconditionally allocate
a temp and expand with tcg_gen_extu_i32_tl. Split out gen_aa32_addr,
gen_aa32_frob64, gen_aa32_ld_i32 and gen_aa32_st_i32 as separate interfaces.
Signed-off-by: Richard Henderson
---
target-arm/translate.c | 171 +
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index cdd61d6..bb2bfee 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -150,17 +150,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc,
From: "Emilio G. Cota"
The exception is not emitted anymore.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-29-git-send-email-c...@braap.org>
---
linux-user/main.c | 93
The v9fs_request() function doesn't use its fmt argument: it passes literal
format strings to proxy_marshal() for all commands.
This patch simply drops the unused fmt argument and updates all callers
accordingly.
Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goater
---
hw/9pfs/9p-proxy.c | 6
From: "Emilio G. Cota"
With this microbenchmark we can measure the overhead of emulating atomic
instructions with a configurable degree of contention.
The benchmark spawns $n threads, each performing $o atomic ops (additions)
in a loop. Each atomic operation is performed on a different cache lin
From: "Emilio G. Cota"
It's been superseded by the atomic helpers.
The use of the atomic helpers provides a significant performance and scalability
improvement. Below is the result of running the atomic_add-test microbenchmark
with:
$ x86_64-linux-user/qemu-x86_64 tests/atomic_add-bench -o 500
TGT_LE and TGT_BE are not size dependent and do not need to be
redefined. The others are no longer used at all.
Signed-off-by: Richard Henderson
---
cputlb.c | 8
softmmu_template.h | 22 --
2 files changed, 8 insertions(+), 22 deletions(-)
diff --git a/
From: "Emilio G. Cota"
[rth: Avoid qemu_load that's redundant with the atomic op.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-15-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 26 --
1 file changed, 20 ins
From: "Emilio G. Cota"
This paves the way for upcoming work.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-9-git-send-email-c...@braap.org>
---
include/qemu/atomic.h | 17 +
1 file changed, 17 insertions(
From: "Emilio G. Cota"
[rth: Avoid redundant qemu_ld in locked case. Fix previously unnoticed
incorrect zero-extension of address in register-offset case.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-18-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
targe
From: "Emilio G. Cota"
[rth: Move redundant qemu_load out of cmpxchg loop.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-16-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 38 ++
1 file changed, 3
Signed-off-by: Richard Henderson
---
cputlb.c | 21 +
softmmu_template.h | 23 ---
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 5575b73..0c9b77b 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -527,6 +527,27 @
Saves 2k code size off of a cold path.
Signed-off-by: Richard Henderson
---
cputlb.c | 37 +
softmmu_template.h | 52 ++--
2 files changed, 47 insertions(+), 42 deletions(-)
diff --git a/cputlb.c b/cpu
From: "Emilio G. Cota"
[rth: Move load of reg value to common location.]
Signed-off-by: Emilio G. Cota
Message-Id: <1467054136-10430-17-git-send-email-c...@braap.org>
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletio
From: "Emilio G. Cota"
The diff here is uglier than necessary. All this does is to turn
FOO
into:
if (s->prefix & PREFIX_LOCK) {
BAR
} else {
FOO
}
where FOO is the original implementation of an unlocked cmpxchg.
[rth: Adjust unlocked cmpxchg to use movcond instead of branches.
Adjust he
We already include exec/address-spaces.h and exec/memory.h in
cputlb.c; the include of qemu/timer.h appears to be a fossil.
Signed-off-by: Richard Henderson
---
softmmu_template.h | 4
1 file changed, 4 deletions(-)
diff --git a/softmmu_template.h b/softmmu_template.h
index 538cff5..b9532a
This is really just a placeholder for an actual
command-line switch for mttcg.
---
translate-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/translate-all.c b/translate-all.c
index 70f3959..c860cfc 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -119,7 +119,7 @@ sta
This adds PCI init code and a basic test that checks the device config
matches what is passed on the command line.
Signed-off-by: Greg Kurz
Acked-by: Cornelia Huck
---
V2: - s/char* tag/char *tag/ (patchew)
- moved "mount_tag" change from 2/3 to 1/3 (Cornelia)
- added Cornelia's A-b tag
Add all of cmpxchg, op_fetch, fetch_op, and xchg.
Handle both endian-ness, and sizes up to 8.
Handle expanding non-atomically, when emulating in serial.
Signed-off-by: Richard Henderson
---
Makefile.objs | 1 -
Makefile.target | 1 +
atomic_template.h | 173
Allows Int128 to be used more generally, rather than having to
begin with 64-bit inputs and accumulate.
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/include/qemu/int128.h b/include/qemu/int128
From: "Emilio G. Cota"
This paves the way for upcoming work.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-8-git-send-email-c...@braap.org>
---
include/qemu/atomic.h | 4
1 file changed, 4 insertions(+)
diff --git
Signed-off-by: Richard Henderson
---
exec.c| 4 ++--
include/qemu/int128.h | 10 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index c8389f9..cc2997e 100644
--- a/exec.c
+++ b/exec.c
@@ -320,9 +320,9 @@ static inline bool section_cover
Signed-off-by: Richard Henderson
---
include/qemu/int128.h | 135 +-
tests/test-int128.c | 22
2 files changed, 145 insertions(+), 12 deletions(-)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 52aaf99..08f1db1 100644
Signed-off-by: Richard Henderson
---
cputlb.c | 16
softmmu_template.h | 7 ++-
2 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 3c99c34..5575b73 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -529,16 +529,16 @@ static bool victim
Rebased on top of Paolo's safe-work series, which means
that we now have cpu_exec_step_atomic for system mode as
well as linux-user. This should fix the problems with
atomic access to notdirty pages that have been reported.
Folded in some feedback from Alex from v3.
A complete tree may be found
First step to be able to run several functional steps.
Signed-off-by: Greg Kurz
Acked-by: Cornelia Huck
---
v2: - moved "mount_tag" change from 2/3 to 1/3 (Cornelia)
- added Cornelia's A-b tag
---
tests/virtio-9p-test.c | 42 +-
1 file changed, 25 i
This series brings some basic functional testing to 9P (only the virtio
part actually).
As with other virtio-* qtests, PC platform is assumed.
This v3 fixes the endianness issue in patch 3/3.
---
Greg Kurz (3):
tests: virtio-9p: introduce start/stop functions
tests: virtio-9p: add b
This adds a simple test to validate the device is functional: it transmits
a request with type Terror, which is not used by the 9P protocol [1], and
expects QEMU to return a reply with type Rerror and the "Operation not
supported" error string.
[1] http://lxr.free-electrons.com/source/include/net/
New arm_regime_tbi0() and arm_regime_tbi0() to extract the TBI values from
the correct TCR for the current EL.
New shift, mask and accessor macro definitions needed to add TBI flag bits
to the TB flags field.
cpu_get_tb_cpu_state() inserst the TBI values into 'flags' parameter
so that they show u
The following changes since commit 5f473241ac595452ae0638dc63e7af2a2294f5ec:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2016-09-15 18:12:40 +0100)
are available in the git repository at:
https://github.com/gkurz/qemu.git tags/for-upstream
for you to fetc
On 09/16/2016 12:13 AM, Benjamin Herrenschmidt wrote:
> On Thu, 2016-09-15 at 14:45 +0200, Cédric Le Goater wrote:
>> This version of the LPC controller model doesn't yet implement
>> support for the SerIRQ deserializer present in the Naples version
>> of the chip though some preliminary work is th
If tagged addresses are enabled, then addresses being loaded into the
PC must be cleaned up by overwriting the tag bits with either all 0's
or all 1's as specified in the ARM ARM spec. The decision process is
dependent on whether the code will be running in EL0/1 or in EL2/3 and
On Fri, 16 Sep 2016 15:46:26 +0100
Peter Maydell wrote:
> On 16 September 2016 at 15:39, Greg Kurz wrote:
> > Ok, I'll look into it... but the important part in this pull request is
> > the "9pfs: fix potential segfault during walk" patch. It fixes a regression
> > introduced in 2.7 by the 9P se
gen_intermediate_code_a64() transfers TBI values from TB->flags to
DisasContext structure.
disas_uncond_b_reg() calls new function gen_a64_set_pc_reg() to handle BR,
BLR and RET instructions.
gen_a64_set_pc_reg() implements all of the required checks and overwiting
logic to clean up the tag field
Certain instructions which can not directly load a tagged address value
may trigger a corner case when the address size is 56 bits. This is
because incrementing or offsetting from the current PC can cause an
arithetic roll-over into the tag bits. Per the ARM ARM spec, these cases
should also be a
On Fri, Sep 16, 2016 at 07:50:23PM +0400, Marc-André Lureau wrote:
> Running cpuid instructions with a simple run like:
> i386-linux-user/qemu-i386 tests/tcg/sha1-i386
>
> Results in the following assert:
> #0 0x764246f5 in raise () from /lib64/libc.so.6
> #1 0x764262fa in abor
On 09/15/16 11:52, Paolo Bonzini wrote:
>
>
> On 07/09/2016 02:48, Thorsten Kohfeldt wrote:
>> From: Thorsten Kohfeldt
>> Date: Wed, 31 Aug 2016 22:43:14 +0200
>> Subject: [PATCH] hmp: Improve 'info mtree' with optional parm for mapinfo
>>
>> Motivation
>> When 'tuning' 'quirks' for VFIO importe
CC Stefan
On 09/15/16 13:34, P J P wrote:
> From: Prasad J Pandit
>
> virtio back end uses set of buffers to facilitate I/O operations.
> If its size is too large, 'cpu_physical_memory_map' could return
> a null address. This would result in a null dereference
> while un-mapping descriptors. Add
This helper is similar to v9fs_string_sprintf(), but it includes the
terminating NUL character in the size field.
This is to avoid doing v9fs_string_sprintf((V9fsString *) &path) and
then bumping the size.
Affected users are changed to use this new helper.
Signed-off-by: Greg Kurz
Reviewed-by:
On Fri, Sep 16, 2016 at 11:06:34AM -0400, Marc-André Lureau wrote:
> Hi
>
> - Original Message -
> > >
> > > -#ifndef CONFIG_USER_ONLY
> > > +#ifdef CONFIG_USER_ONLY
> > > +cs->nr_cores = smp_cores;
> > > +cs->nr_threads = smp_threads;
> > > +#else
> >
> > On CONFIG_USER_ONLY, s
On Thu, 2016-09-15 at 17:20 +0300, Marcel Apfelbaum wrote:
> > Just catching up on mail after vacation and read this thread. Thanks
> > Marcel for writing this document (I guess a v1 is coming soon).
>
> Yes, I am sorry but I got caught up with other stuff and I am
> going to be in PTO for a week,
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