On 09/16/2016 12:13 AM, Benjamin Herrenschmidt wrote:
> On Thu, 2016-09-15 at 14:45 +0200, Cédric Le Goater wrote:
>> This version of the LPC controller model doesn't yet implement
>> support for the SerIRQ deserializer present in the Naples version
>> of the chip though some preliminary work is there.
>
> The version in my branch has this support btw.
Yes. there is some of it in patch 10 :
+ if (pcc->chip_type == PNV_CHIP_POWER8NVL) {
+ irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, 16);
+ } else {
+ irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, NULL, 16);
+ }
but these are empty shell for the moment as I need PSI, and so XICS
native, to go forward. Working on it.
Cheers,
C.
