On 02/12/2015 04:44 PM, Fam Zheng wrote:
> On Thu, 02/12 15:40, Wen Congyang wrote:
>> On 02/12/2015 03:21 PM, Fam Zheng wrote:
>>> Hi Congyang,
>>>
>>> On Thu, 02/12 11:07, Wen Congyang wrote:
+== Workflow ==
+The following is the image of block replication workflow:
+
+
Tilegx Qemu can decode bundle, disassemble code, and generate tcg code
for 1st TB block (__start). Then directly jump to __libc_start_main (2nd
TB block).
In __libc_start_main, tilegx qemu continues executing, and reach to the
indirectly jump statement, and jump to 3rd TB block correctly.
The rel
On Mon, Feb 23, 2015 at 11:03 PM, Jan Kiszka wrote:
> No new features yet, just encapsulation.
>
> Signed-off-by: Jan Kiszka
Reviewed-by: Peter Crosthwaite
> ---
>
> Changes in v4:
> - fixed up type name as Peter suggested
>
> hw/arm/integratorcp.c | 35 +++
>
On Thu, 12 Feb 2015 15:50:34 -0200
Eduardo Habkost wrote:
> Each CPU can appear in only one NUMA node on the NUMA config. Reject
> configuration if a CPU appears in multiple nodes.
>
> Signed-off-by: Eduardo Habkost
> ---
> v1 -> v2: (no changes)
>
> v2 -> v3:
> * Rename present_cpus to seen_
No new features yet, just encapsulation.
Signed-off-by: Jan Kiszka
---
Changes in v4:
- fixed up type name as Peter suggested
hw/arm/integratorcp.c | 35 +++
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integrato
On Mon, Feb 23, 2015 at 02:26:28PM -0700, Eric Blake wrote:
> > -- "tls": whevener the channel is encrypted (json-bool)
> > +- "tls": whenever the channel is encrypted (json-bool)
>
> Might be nicer as 'whether' rather than 'whenever'.
Oh, you're right. Feel free to change it, or do you want me
On Thu, 12 Feb 2015 15:50:33 -0200
Eduardo Habkost wrote:
> CPU index is always less than max_cpus, as documented at sysemu.h:
>
> > The following shall be true for all CPUs:
> > cpu->cpu_index < max_cpus <= MAX_CPUMASK_BITS
>
> Reject configuration which uses invalid CPU indexes.
>
> Signed
Am 23.02.2015 um 19:59 schrieb Max Reitz:
On 2015-02-23 at 09:27, Peter Lieven wrote:
The VHD spec [1] allows for total_sectors of 65535 x 16 x 255 (~127GB)
represented by a CHS geometry. If total_sectors is greater
than 65535 x 16 x 255 this geometry is set as a maximum.
Qemu, Hyper-V, Virtual
Am 23.02.2015 um 19:34 schrieb Max Reitz:
On 2015-02-23 at 09:27, Peter Lieven wrote:
From: Kevin Wolf
The CHS calculation as done per the VHD spec imposes a maximum image
size of ~127 GB. Real VHD images exist that are larger than that.
Apparently there are two separate non-standard ways to
Am 23.02.2015 um 19:29 schrieb Max Reitz:
On 2015-02-23 at 09:27, Peter Lieven wrote:
Signed-off-by: Peter Lieven
---
block/vpc.c | 116 +++
1 file changed, 52 insertions(+), 64 deletions(-)
diff --git a/block/vpc.c b/block/vpc.c
inde
Am 23.02.2015 um 19:08 schrieb Max Reitz:
On 2015-02-23 at 09:27, Peter Lieven wrote:
*pnum can't be greater than s->block_size / BDRV_SECTOR_SIZE for allocated
sectors since there is always a bitmap in between.
Signed-off-by: Peter Lieven
---
block/vpc.c | 15 ++-
1 file chan
Am 23.02.2015 um 18:10 schrieb Max Reitz:
On 2015-02-23 at 10:01, Peter Lieven wrote:
VHD images contain a bitmap at the beginning of each data block
to indicate the allocation status of each sector in the data block.
vpc_read currently checks the allocation status of the first sector
in a data
On Thu, 12 Feb 2015 15:50:32 -0200
Eduardo Habkost wrote:
> Fix the CPU index check to ensure we don't go beyond the size of the
> node_cpu bitmap.
>
> CPU index is always less than MAX_CPUMASK_BITS, as documented at
> sysemu.h:
>
> > The following shall be true for all CPUs:
> > cpu->cpu_ind
On Mon, Feb 23, 2015 at 3:05 PM, David Gibson
wrote:
> Currently the ivshmem device is built whenever both PCI and KVM support are
> included. This patch gives it its own config option to allow easier
> customization of whether to include it. It's enabled by default in the
> same circumstances a
On Mon, Feb 23, 2015 at 3:05 PM, David Gibson
wrote:
> Currently the "platform-bus" device is included for all softmmu builds.
> This bridge is intended for use on any platforms that require dynamic
> creation of sysbus devices. However, at present it is used only for the
> PPC E500 target, with
On Thu, Jan 08, 2015 at 11:40:20AM +0530, Bharata B Rao wrote:
> Make use of pc-dimm infrastructure to support memory hotplug
> for PowerPC.
>
> Modelled on i386 memory hotplug.
>
> Signed-off-by: Bharata B Rao
> ---
> hw/ppc/spapr.c| 107
> +
On Mon, Feb 23, 2015 at 3:05 PM, David Gibson
wrote:
> The i82801b11, ioh3420 and xio3130 PCI Express devices are currently
> included in the build unconditionally.
>
> While they could theoretically appear on any target platform with PCI-E,
> they're pretty unlikely to appear on platforms that ar
The subject should read V2 as this is a resubmit. Use git format-patch
--subject-prefix="PATCH v2".
On Mon, Feb 23, 2015 at 4:29 PM, Jorge Acereda Maciá wrote:
> Please, forget my previous patch, worked somehow with Chrome but failed with
> Safari (with a good reason, the sent headers were incor
On Mon, Feb 23, 2015 at 07:34:00PM +1100, Alexey Kardashevskiy wrote:
> Useful for debugging.
>
> Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
> ---
> hw/ppc/spapr_iommu.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/ppc/spapr_iommu.c b/hw/p
On Mon, Feb 23, 2015 at 07:33:59PM +1100, Alexey Kardashevskiy wrote:
> This replaces object_child_foreach() and callback with existing
> SPAPR_PCI_LIOBN() and spapr_tce_find_by_liobn() to make the code easier
> to read.
>
> This is a mechanical patch so no behaviour change is expected.
>
> Signe
On Mon, Feb 23, 2015 at 07:33:55PM +1100, Alexey Kardashevskiy wrote:
> This gets rid of a magic constant describing the default DMA window size
> for an emulated PHB.
>
> Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
--
David Gibson| I'll have my music bar
On Mon, Feb 23, 2015 at 07:22:52PM +1100, Alexey Kardashevskiy wrote:
> This moves SPAPR bits to a separate file to avoid pollution of x86 code.
>
> This is a mechanical patch.
>
> Signed-off-by: Alexey Kardashevskiy
This seems sensible to me.
Reviewed-by: David Gibson
> ---
>
> There is an
On Mon, Feb 23, 2015 at 07:33:56PM +1100, Alexey Kardashevskiy wrote:
> This is to reduce VIO noise while debugging PCI DMA.
>
> Signed-off-by: Alexey Kardashevskiy
So, in terms of mechanical correctness:
Reviewed-by: David Gibson
I see the rationale, but the idea of conditional tracepoints s
** Also affects: qemu
Importance: Undecided
Status: New
** Changed in: qemu (Ubuntu)
Status: New => Confirmed
** Changed in: qemu (Ubuntu)
Importance: Undecided => Wishlist
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed
** Also affects: qemu
Importance: Undecided
Status: New
** Also affects: qemu (Ubuntu)
Importance: Undecided
Status: New
** Changed in: qemu (Ubuntu)
Importance: Undecided => Medium
** Changed in: qemu (Ubuntu)
Status: New => Confirmed
--
You received this bug not
On 02/24/2015 04:43 AM, Max Reitz wrote:
> On 2015-02-11 at 22:07, Wen Congyang wrote:
>> We connect to NBD server when starting block replication, so
>> the length is 0 before starting block replication.
>>
>> Signed-off-by: Wen Congyang
>> Signed-off-by: zhanghailiang
>> Signed-off-by: Gonglei
On Tue, Feb 24, 2015 at 9:04 AM, Peter Crosthwaite
wrote:
> Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
>
> Signed-off-by: Peter Crosthwaite
> ---
> hw/arm/xlnx-zynq-mp-generic.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/arm/xlnx-zynq-mp-generic.c
Hi Igor, Andreas,
Could you please help to review this version?
Thanks,
Gu
On 02/13/2015 06:40 PM, Zhu Guihua wrote:
> This series is based on chen fan's previous i386 cpu hot remove patchset:
> https://lists.nongnu.org/archive/html/qemu-devel/2013-12/msg04266.html
>
> Via implementing ACPI sta
Hi Igor, Andreas,
The issues you commented in the previous version have been fixed in this one.
Could you please help to review it?
Regards,
Gu
On 02/13/2015 06:25 PM, Zhu Guihua wrote:
> This series is based on the previous patchset from Chen Fan:
> https://lists.nongnu.org/archive/html/qemu-de
On Mon, Feb 23, 2015 at 4:21 AM, Jan Kiszka wrote:
> This allows to use the SD card emulation of the board: Forward the
> signals from the pl181 top the CP control register emulation, report the
> current state via CP_INTREG, deliver CARDIN IRQ to the secondary
> interrupt controller and also supp
On Mon, Feb 23, 2015 at 4:21 AM, Jan Kiszka wrote:
> No new features yet, just encapsulation.
>
> Signed-off-by: Jan Kiszka
> ---
> hw/arm/integratorcp.c | 35 +++
> 1 file changed, 27 insertions(+), 8 deletions(-)
>
> diff --git a/hw/arm/integratorcp.c b/hw/arm/i
Allow the user to poll until a desired interrupt occurs.
Signed-off-by: John Snow
---
tests/ide-test.c | 11 +--
tests/libqtest.c | 16
tests/libqtest.h | 20
3 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/tests/ide-test.c b/tests/i
Signed-off-by: John Snow
---
tests/ahci-test.c | 44
1 file changed, 44 insertions(+)
diff --git a/tests/ahci-test.c b/tests/ahci-test.c
index d43da45..f194cbc 100644
--- a/tests/ahci-test.c
+++ b/tests/ahci-test.c
@@ -46,6 +46,7 @@
/*** Globals **
Signed-off-by: John Snow
---
tests/ahci-test.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/tests/ahci-test.c b/tests/ahci-test.c
index f536b19..378cfe5 100644
--- a/tests/ahci-test.c
+++ b/tests/ahci-test.c
@@ -774,6 +774,29 @@ static void ahci_test_io_
Signed-off-by: John Snow
---
tests/ahci-test.c| 67
tests/libqos/libqos-pc.c | 5
tests/libqos/libqos-pc.h | 1 +
3 files changed, 51 insertions(+), 22 deletions(-)
diff --git a/tests/ahci-test.c b/tests/ahci-test.c
index 378cfe5..d
Add qmp_async, which lets us send QMP commands asynchronously.
This is useful when we want to send commands that will trigger
event responses, but we don't know in what order to expect them.
Sometimes the event responses may arrive even before the command
confirmation will show up, so it is conven
This series requires, in order:
ahci-preliminary-refactor (stefanha/block)
ahci-dma-test (stefanha/block)
[PATCH v4 00/17] ide: rerror/werror migration fixes for IDE/ISA and AHCI
[PATCH 0/8] ahci: add more IO tests
This patchset brings us up to feature parity with the ide-test that
wa
Pull this helper out of ide-test and into libqos,
to be shared with ahci-test.
Signed-off-by: John Snow
---
tests/ide-test.c | 23 +--
tests/libqos/libqos.c | 22 ++
tests/libqos/libqos.h | 1 +
3 files changed, 24 insertions(+), 22 deletions(-)
dif
Please, forget my previous patch, worked somehow with Chrome but failed with
Safari (with a good reason, the sent headers were incorrect). This one should
be correct and simpler.
Signed-off-by: Jorge Acereda Macia
---
ui/vnc-ws.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff -
Using standard ARM bootloader.
Signed-off-by: Peter Crosthwaite
---
hw/arm/xlnx-zynq-mp-generic.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/xlnx-zynq-mp-generic.c b/hw/arm/xlnx-zynq-mp-generic.c
index 7394e82..a86f10d 100644
--- a/hw/arm/xlnx-zynq-mp-generic.c
+++ b/hw/a
The i82801b11, ioh3420 and xio3130 PCI Express devices are currently
included in the build unconditionally.
While they could theoretically appear on any target platform with PCI-E,
they're pretty unlikely to appear on platforms that aren't Intel derived.
Therefore, to avoid presenting unlikely-to
To allow using the device with modern SoC programming conventions. The
state struct needs to be visible to embed the device in SoC containers.
Signed-off-by: Peter Crosthwaite
---
hw/net/cadence_gem.c | 43 +-
include/hw/net/cadence_gem.h | 49
This series adds explicit config options to control inclusion of a
number of devices. These are generally things that could
theoretically appear on anything (or at least a wide range of
targets), but are in practice only likely to appear on a much smaller
set of targets.
In some cases the set of
And connect IRQ outputs to the CPUs.
Signed-off-by: Peter Crosthwaite
---
hw/arm/xlnx-zynq-mp.c | 19 +++
include/hw/arm/xlnx-zynq-mp.h | 2 ++
2 files changed, 21 insertions(+)
diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
index d553fb0..9cdff13 100644
---
Currently the ivshmem device is built whenever both PCI and KVM support are
included. This patch gives it its own config option to allow easier
customization of whether to include it. It's enabled by default in the
same circumstances as now - when both PCI and KVM are available.
Signed-off-by: D
There are 2x Cadence UARTSs in Zynq MP. Add them.
Signed-off-by: Peter Crosthwaite
---
hw/arm/xlnx-zynq-mp.c | 21 +
include/hw/arm/xlnx-zynq-mp.h | 3 +++
2 files changed, 24 insertions(+)
diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
index 2ef57d9..9d
With quad Cortex-A53 CPUs.
Signed-off-by: Peter Crosthwaite
---
default-configs/aarch64-softmmu.mak | 2 +-
hw/arm/Makefile.objs| 1 +
hw/arm/xlnx-zynq-mp.c | 71 +
include/hw/arm/xlnx-zynq-mp.h | 21 +++
4 files c
Currently the "platform-bus" device is included for all softmmu builds.
This bridge is intended for use on any platforms that require dynamic
creation of sysbus devices. However, at present it is used only for the
PPC E500 target, with plans for the ARM "virt" target in the immediate
future.
To a
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Signed-off-by: Peter Crosthwaite
---
hw/arm/xlnx-zynq-mp-generic.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/xlnx-zynq-mp-generic.c b/hw/arm/xlnx-zynq-mp-generic.c
index ff69b07..7394e82 100644
--- a/hw/ar
There are 4x Cadence GEMs in Zynq MP. Add them.
Signed-off-by: Peter Crosthwaite
---
hw/arm/xlnx-zynq-mp.c | 32
include/hw/arm/xlnx-zynq-mp.h | 3 +++
2 files changed, 35 insertions(+)
diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
index be
In preparation for migrating the state struct and type cast macro to a public
header. The acronym "GEM" on it's own is not specific enough to be used in a
more global namespace so preface with "cadence". Fix the capitalisation of
"gem" in the state type while touching the typename. Also preface the
Add a generic machine for the Xilinx Zynq MP SoC. This is a minimal
machine that exposes the capabilities of the raw SoC as a usable
machine.
Signed-off-by: Peter Crosthwaite
---
hw/arm/Makefile.objs | 2 +-
hw/arm/xlnx-zynq-mp-generic.c | 52 +++
Use SMC PSCI, with the standard policy of secondaries starting in
power-off.
Signed-off-by: Peter Crosthwaite
---
hw/arm/xlnx-zynq-mp.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
index 9d7e834..0952221 100644
--- a/hw/arm/xlnx-zynq-m
To allow using the device with modern SoC programming conventions. The
state struct needs to be visible to embed the device in SoC containers.
Signed-off-by: Peter Crosthwaite
---
hw/char/cadence_uart.c | 29 +
include/hw/char/cadence_uart.h | 35 +
Similar to a53, but with different L1 I cache policy, phys addr size and
different cache geometries. The cache sizes is implementation
configurable, but use these values (from Xilinx MPSoC) as a default
until cache size configurability is added.
Signed-off-by: Peter Crosthwaite
---
target-arm/cp
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
machine model.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs are added. The
pre-existing models for GEM and UART are not SoC friendly
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Signed-off-by: Peter Crosthwaite
---
hw/arm/xlnx-zynq-mp.c | 16
1 file changed, 16 insertions(+)
diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
index 9cdff13..be82a66 100644
--- a/hw/arm/x
In preparation for support for Cortex a53. Use "axx" to describe the
shareable features. Some of the CP15 registers (such as ACTLR) are
specific to implementation, but we currently just RAZ them so continue
with that as the policy for all cortex A processors under a shared
definition.
The cache si
In preparation for migrating the state struct and type cast macro to a public
header. The acronym "UART" on it's own is not specific enough to be used in a
more global namespace so preface with "cadence". Fix the capitalisation of
"uart" in the state type while touching the typename. Preface macros
s->blocker is really only used in hw/scsi/virtio-scsi.c; the only places
where it is used in hw/scsi/virtio-scsi-dataplane.c is when it is
allocated and when it is freed. That does not make a whole lot of sense
(and is actually wrong because this leads to s->blocker potentially
being NULL when blk_
On Mon, Feb 16, 2015 at 6:43 AM, Ryota Ozaki wrote:
> Signed-off-by: Ryota Ozaki
> Reviewed-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
> ---
> target-arm/cpu64.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index 823c739..270bc2f
On 02/23/2015 05:35 PM, Marc Marí wrote:
El Mon, 23 Feb 2015 17:22:57 -0500
John Snow escribió:
I've been seeing this failure pop up very occasionally and I can
usually get the test to pass again by just re-running, but every now
and again:
GTESTER check-qtest-x86_64
blkdebug: Suspended requ
On 2015-02-11 at 22:07, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block/Makefile.objs | 2 +-
block/blkcolo.c | 409
2 files changed, 410 insertions(+), 1 deletion(-)
El Mon, 23 Feb 2015 17:22:57 -0500
John Snow escribió:
> I've been seeing this failure pop up very occasionally and I can
> usually get the test to pass again by just re-running, but every now
> and again:
>
> GTESTER check-qtest-x86_64
> blkdebug: Suspended request 'A'
> blkdebug: Resuming reque
On 2015-02-11 at 22:07, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block/Makefile.objs| 1 +
block/blkcolo-buffer.c | 324 +
block/blkcolo.h| 35 ++
3 files chan
I've been seeing this failure pop up very occasionally and I can usually
get the test to pass again by just re-running, but every now and again:
GTESTER check-qtest-x86_64
blkdebug: Suspended request 'A'
blkdebug: Resuming request 'A'
main-loop: WARNING: I/O thread spun for 1000 iterations
main-
On 2015-02-11 at 22:07, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
I don't think this is a good idea. With this patch, every time you open
a COW file (with a bac
On 2015-02-11 at 22:07, Wen Congyang wrote:
Block replication needs this feature.
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block.c | 2 ++
include/block/block_int.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/block.c
On 02/23/2015 01:57 PM, Max Reitz wrote:
> On 2015-02-11 at 22:07, Wen Congyang wrote:
>> Signed-off-by: Wen Congyang
>> Signed-off-by: zhanghailiang
>> Signed-off-by: Gonglei
>> ---
>> block.c | 36
>> include/block/block.h | 10
On 02/11/2015 08:07 PM, Wen Congyang wrote:
> To block replication, we only need to read from the first child.
s/quorom/quorum/ in the subject line
s/To block/For block/
>
> Signed-off-by: Wen Congyang
> Signed-off-by: zhanghailiang
> Signed-off-by: Gonglei
> Cc: Luiz Capitulino
> Cc: Micha
On 2015-02-11 at 22:07, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
Our current stance on BlockBackends is (as far as I know, anyway) that a
BlockBackend
On 2015-02-11 at 22:07, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block/block-backend.c | 29 -
include/sysemu/block-backend.h | 2 ++
2 files changed, 30 insertions(+), 1 deletion(-)
Hm,
On 2015-02-11 at 22:07, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block/nbd.c | 55 +++
1 file changed, 55 insertions(+)
So by now to me it looks like you're using bdrv_start_
On 2015-02-11 at 22:07, Wen Congyang wrote:
The secondary qemu starts later than the primary qemu, so we
cannot connect to nbd server in bdrv_open().
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block/nbd.c | 100 +++
On 02/23/2015 01:27 PM, Alberto Garcia wrote:
> Signed-off-by: Alberto Garcia
> ---
> qmp-commands.hx | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> @@ -2922,7 +2922,7 @@ Channels are described by a json-object, each one
> contain the following:
> - "channel-id": channel id
On 2015-02-11 at 22:07, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block/quorum.c | 69 ++
1 file changed, 69 insertions(+)
diff --git a/block/quorum.c b/block/quorum.c
inde
On 02/23/2015 10:40 AM, Markus Armbruster wrote:
>>> int64_t pow2floor(int64_t value)
>>> {
>>> assert(value > 0);
>>> return 0x8000u >> clz64(value);
>>> }
>>
>> Needs to be 0x8000ull for 32-bit machines to compile correctly.
>
> Why?
Because 0x8000u
On 2015-02-11 at 22:07, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block.c | 36
include/block/block.h | 10 ++
include/block/block_int.h | 12
3 fi
On 2015-02-11 at 22:07, Wen Congyang wrote:
We connect to NBD server when starting block replication, so
the length is 0 before starting block replication.
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
block/quorum.c | 5 +
1 file changed, 5 insert
On 2015-02-11 at 22:07, Wen Congyang wrote:
To block replication, we only need to read from the first child.
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
Cc: Luiz Capitulino
Cc: Michael Roth
---
block/quorum.c | 5 +++--
qapi/block-core.json | 4 +
Signed-off-by: Alberto Garcia
---
qmp-commands.hx | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/qmp-commands.hx b/qmp-commands.hx
index a85d847..52741ed 100644
--- a/qmp-commands.hx
+++ b/qmp-commands.hx
@@ -1,5 +1,5 @@
HXCOMM QMP dispatch table and documentation
-HXC
Ping? Can somebody help review this?
On Thu, Feb 12, 2015 at 03:50:31PM -0200, Eduardo Habkost wrote:
> This adds extra checks to the NUMA code to make sure the CPU configuration is
> consistent. This needs to be applied on top of the following series:
>
> Message-Id: <1423421482-11619-1-git-se
On 2015-02-23 at 09:27, Peter Lieven wrote:
the field is named current size in the spec. Name it accordingly.
Signed-off-by: Peter Lieven
---
block/vpc.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Max Reitz
On 02/23/2015 12:03 PM, Max Reitz wrote:
On 2015-02-20 at 18:07, John Snow wrote:
Signed-off-by: John Snow
---
block.c| 20
include/block/block.h | 1 +
include/qemu/hbitmap.h | 10 ++
util/hbitmap.c | 47
On 2015-02-23 at 09:27, Peter Lieven wrote:
The VHD spec [1] allows for total_sectors of 65535 x 16 x 255 (~127GB)
represented by a CHS geometry. If total_sectors is greater
than 65535 x 16 x 255 this geometry is set as a maximum.
Qemu, Hyper-V, VirtualBox and disk2vhd use this special geometry
From: Paolo Bonzini
Resetting the io_buffer_index to 0 is commonized,
with the exception of the case within ide_atapi_cmd_reply,
where we need to reset this index to 0 prior to the
ide_atapi_cmd_reply_end call.
Note that not all calls to ide_atapi_cmd_reply_end
expect the index to be 0, so setti
From: "Michael S. Tsirkin"
It's not easy to figure out how monitor translates
strings: most QEMU code deals with translated indexes,
these are translated using _lookup arrays,
so you need to find the array name, and find the
appropriate offset.
This patch adds C99 indexes to lookup arrays, which
Amazingly, we weren't doing this before.
Make sure we migrate the IDEState structure that belongs to
the AHCIDevice.IDEBus structure during migrations.
No version numbering changes because AHCI is not officially
migratable (and we can all see with good reason why) so we
do not impact any official
From: Paolo Bonzini
Signed-off-by: Paolo Bonzini
Signed-off-by: John Snow
---
hw/ide/isa.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ide/isa.c b/hw/ide/isa.c
index b084162..5eb35c2 100644
--- a/hw/ide/isa.c
+++ b/hw/ide/isa.c
@@ -74,7 +74,8 @@ static void isa_ide
When the AHCI HBA device is migrated, all of the information that
led to the request being created is stored in the AHCIDevice
structures, except for pointers into guest data where return
information needs to be stored.
The "cur_cmd" field is usually responsible for this.
To rebuild the cur_cmd p
From: Paolo Bonzini
This is easy, since start_dma already restarts processing from the
beginning of the PRDT.
Migration is also easy to cover; the comment about busy_slot is
wrong, busy_slot will only be set if there is an error. In this
case we have nothing to do really. The core IDE code wil
From: Paolo Bonzini
With restarts now handled by ide_restart_cb and
the IDEDMAOps.restart_dma() member, remove the old
restart_cb callback.
Signed-off-by: Paolo Bonzini
Signed-off-by: John Snow
---
hw/ide/ahci.c | 5 -
hw/ide/core.c | 5 -
hw/ide/internal.h | 1 -
hw/ide/macio
From: Paolo Bonzini
Signed-off-by: Paolo Bonzini
Signed-off-by: John Snow
---
hw/ide/core.c | 12
hw/ide/internal.h | 4
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index ff28db0..ef52f35 100644
--- a/hw/ide/core.c
+++ b/h
From: Paolo Bonzini
With BMDMA specific excised from the restart functions,
create a HBA-agnostic restart callback to be shared
between the different HBAs.
Change the callback registered with the vmstate_change
handler to always point to ide_restart_cb instead of
relying on the IDEDMAOps.restart
From: Paolo Bonzini
This only breaks backwards migration compatibility if the bus is in
an error state. It is in principle possible to avoid this by making
two subsections (one for version 1, and one for version 2, but with
the same name) with different "_needed" callbacks. The v1 callback woul
This patch adds tests for werror and rerror functionality
for the PCI and ISA ide buses.
Tests for the AHCI device are to be included at a later
date after requisite patches have been merged upstream
to support needed functionality by the tests.
Signed-off-by: Paolo Bonzini
Signed-off-by: John S
From: Paolo Bonzini
Pass the containing IDEBus to the restart_cb instead
of the more specific BMDMAState child.
Signed-off-by: Paolo Bonzini
Signed-off-by: John Snow
---
hw/ide/core.c | 2 +-
hw/ide/pci.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/ide
From: Paolo Bonzini
This patch adds the restart_dma callback and adjusts
the ide_restart_dma function to utilize this callback
to call the BMDMA-specific restart code instead of statically
executing BMDMA-specific code.
Signed-off-by: Paolo Bonzini
Signed-off-by: John Snow
---
hw/ide/internal
From: Paolo Bonzini
Start moving the initial state of the current request to IDEBus, so that
AHCI can use it. The set_unit callback is not used anymore once this is
done.
Signed-off-by: Paolo Bonzini
Signed-off-by: John Snow
---
hw/ide/ahci.c | 7 ---
hw/ide/core.c | 6 --
From: Paolo Bonzini
A helper is added that registers the IDEDMAOp .restart_cb()
via qemu_add_vm_change_state_handler instead of requiring
each HBA to register the callback themselves.
Signed-off-by: Paolo Bonzini
Signed-off-by: John Snow
---
hw/ide/cmd646.c | 3 +--
hw/ide/core.c | 5 ++
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