On Mon, Feb 17, 2014 at 12:42:45AM +0100, Paolo Bonzini wrote:
> Il 15/02/2014 19:10, Michael Tokarev ha scritto:
> > 13 февраля 2014 г. 16:03:12 GMT+04:00, Antonios Motakis
> > пишет:
> >> Extend -mem-path with additional properties:
> >>
> >> - prealloc=on|off - default off, same as -mem-preall
As reported in
http://article.gmane.org/gmane.comp.emulators.qemu/253987
Mac OSX actually requires describing all occupied slots
in ACPI - even if hotplug isn't enabled.
I didn't expect this so I dropped description of all
non hotpluggable slots from ACPI.
As a result: before
commit 99fd437dee4686
On 02/06/2014 08:26 PM, Dr. David Alan Gilbert wrote:
Hi Isaku,
I hit a seg in qemu_rdma_cleanup in the code changed by your
'[PATCH] rdma: clean up of qemu_rdma_cleanup()'
migration-rdma.c ~ 2241
if (rdma->qp) {
rdma_destroy_qp(rdma->cm_id);
rdma->qp = NULL;
}
Stefan Fritsch just fixed a virtio-net driver bug [1], virtio-net won't
filter out VLAN-tagged packets if VIRTIO_NET_F_CTRL_VLAN isn't negotiated.
We should also not send the vlan table to management, this patch makes
the vlan-talbe optional.
[1] http://lists.nongnu.org/archive/html/qemu-devel/20
PetiteCloud is a layer 0 cloud platform (see site for details of what that
means and how it fits into the virtualization/cloud computing land scape)
that supports among other hypervisors (I know qemu hates the term but
that's what everyone else calls) QEMU. How do I go about getting a link
on qem
于 2014/2/14 17:23, Markus Armbruster 写道:
Wenchao Xia writes:
于 2014/2/13 23:14, Markus Armbruster 写道:
Wenchao Xia writes:
It will check whether the values specified are written correctly,
and whether all enum values are covered, when discriminator is a
pre-defined enum type
Signed-off-by:
This patch implements the ARM PMCCNTR register including
the disable and reset components of the PMCR register.
Signed-off-by: Alistair Francis
---
This patch assumes that non-invasive debugging is not permitted
when determining if the counter is disabled
V6: Rebase to include Peter Maydell's 'Co
What's up with the broken build slaves? What changed over a week ago
that has resulted in a bunch of them failing to work at all?
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On Sun, Feb 16, 2014 at 2:07 AM, Peter Maydell wrote:
> Implement the DAIF system register which is a view of the
> DAIF bits in PSTATE.
>
> Signed-off-by: Peter Maydell
> Reviewed-by: Peter Crosthwaite
> ---
> target-arm/helper.c | 24
> 1 file changed, 24 insertions(+
Il 15/02/2014 19:10, Michael Tokarev ha scritto:
> 13 февраля 2014 г. 16:03:12 GMT+04:00, Antonios Motakis
> пишет:
>> Extend -mem-path with additional properties:
>>
>> - prealloc=on|off - default off, same as -mem-prealloc
>> - share=on|off - default off, memory is mmapped with MAP_SHARED
>
>
The S24/TCX framebuffer is a mildly accelerated video card, with
blitter, stippler and hardware cursor.
* Solaris and NetBSD 6.x use all the hardware acceleration features.
* The Xorg driver (used by Linux) can use the hardware cursor only.
This patch implements hardware acceleration in both 8bit
This patch adds hardware acceleration to QEMU's existing TCX
emulation. Some features (the hardware cursor particularly) depends
on properties set by OpenBIOS.
Here is, for testing, the corresponding OpenBIOS TCX forth driver.
These modifications are not yet comitted into OpenBIOS trunk.
OpenBIO
The Sun4m architecture has one 'system' timer and one timer per CPU.
The CPU timers can be configured in two modes :
* 22bits Counter/Timer. Periodic interrupts.
* 54bits User timer. For profiling. In this mode, the Run/Stop bit
controls the timer.
The run/stop bit controls the timer only when
Two small fixes for the ESP (AM53C94) SCSI controller
* Signal the end of the DMA transfer after a SCSI command.
* The status register (RSTAT) is cleared after reading the interrupt
status register (RINTR), except for the TC bit (=Count To Zero) and the
scsi phase bits, which mirror SCSI signals
Ping.
Repost !
On 30/12/2013 15:02, Artyom Tarasenko wrote:
On Mon, Dec 30, 2013 at 12:51 AM, Olivier Danet wrote:
On SparcStations, the HostID field in the NVRAM is equal to the
last three bytes of the MAC address (which is also stored in the NVRAM).
This constant is used as an identificatio
On 26/01/14 1:06 PM, Paolo Bonzini wrote:
Il 26/01/2014 02:37, Brad Smith ha scritto:
Reviewed-by: Stefan Hajnoczi
Is there some sort of process I am missing to have build fixes
commited so that QEMU actually builds?
Right now we have problems getting patches committed at all.
This patc
On 30 January 2014 08:00, Markus Armbruster wrote:
> Peter Maydell writes:
>> [MacOSX doesn't pull in common symbols from .o files in
>> .a archives]
> Not ugly, but a sensible move (in my opinion) regardless of this
> specific issue: compile with -fno-common. Then both become not common.
>
> `
On Fri, Jan 31, 2014 at 08:47:03AM -0600, Richard Henderson wrote:
> Recognize 0 operand to andc, and -1 operands to and, orc, eqv.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 39 ---
> 1 file changed, 24 insertions(+), 15 deletions(-)
>
> d
On Fri, Jan 31, 2014 at 08:47:02AM -0600, Richard Henderson wrote:
> Like we already do for SUB and XOR.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index cdfc746..a703f8c 100644
> --- a/t
Add the remainder of the 64x64->128 operations in the three-reg-diff
category except for PMULL, PMULL2.
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 109 -
1 file changed, 88 insertions(+), 21 deletions(-)
diff --git a/target-arm/tran
Implement the wide three-reg-different operations:
SADDW, UADDW, SSUBW and USUBW.
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/tran
On Fri, Jan 31, 2014 at 08:47:01AM -0600, Richard Henderson wrote:
> Given, of course, an appropriate constant. These could be generated
> from the "canonical" operation for inversion on the guest, or via
> other optimizations.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 57 ++
Implement the unprivileged load and store instructions.
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 69 +-
1 file changed, 37 insertions(+), 32 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 1
Implement the narrowing three-reg-diff operations: ADDHN,
RADDHN, SUBHN and RSUBHN.
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 60 +-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-a
Another patchset of random filling in the gaps in our Neon
coverage. Patches 1 through 5 complete our handling of the
three-reg-different category of Neon instructions.
Patch 6 implements the "unprivileged load/store" LDTR/STTR
instructions. (In fact AArch64 Linux doesn't use these, and they're
pr
The opcode switch in disas_simd_three_reg_diff() is missing the
customary comments indicating which cases correspond to which
instructions. Add them.
Signed-off-by: Peter Maydell
---
target-arm/translate-a64.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff -
Implement the PMULL instruction; this is the last unimplemented insn
in the three-reg-diff group.
Note that PMULL with size 3 is considered part of the AES part
of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition
in the v8 ARM ARM), so it isn't necessary to burn an extra feature
On Fri, Jan 31, 2014 at 08:47:00AM -0600, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index d3b099a..3291a08 100644
> --- a/tcg/optimize.c
> +++ b/tcg/op
On Fri, Jan 31, 2014 at 08:43:38AM -0600, Richard Henderson wrote:
> These three-operand shift instructions do not require the shift count
> to be placed into ECX. This reduces the number of mov insns required,
> with the mere addition of a new register constraint.
>
> Don't attempt to get rid of
On Fri, Jan 31, 2014 at 08:43:37AM -0600, Richard Henderson wrote:
> Note that the optimizer cannot simplify ANDC X,Y,C to AND X,Y,~C
> so we must handle constants in the implementation of andc.
I do wonder if it actually won't be a better idea to add this
simplification to the optimizer instead o
On Fri, Jan 31, 2014 at 08:43:35AM -0600, Richard Henderson wrote:
> These are not needed by users of tcg-target.h. No need to recompile
> when we adjust them.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/i386/tcg-target.c | 4
> tcg/i386/tcg-target.h | 3 ---
> 2 files changed, 4 inse
On Fri, Jan 31, 2014 at 08:43:36AM -0600, Richard Henderson wrote:
> Prepare for emitting BMI insns which require VEX encoding.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/i386/tcg-target.c | 41 ++---
> 1 file changed, 38 insertions(+), 3 deletions(-)
>
On Fri, Jan 31, 2014 at 08:43:34AM -0600, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> disas/i386.c | 146
> +--
> 1 file changed, 132 insertions(+), 14 deletions(-)
>
> diff --git a/disas/i386.c b/disas/i386.c
> ind
On 02/16/2014 06:21 AM, Paolo Bonzini wrote:
> Il 31/01/2014 15:43, Richard Henderson ha scritto:
>> +gen_shift_maybe_vex:
>> +if (have_bmi2 && !const_args[2]) {
>> +tcg_out_vex_modrm(s, vexop + rexw, args[0], args[2], args[1]);
>> +break;
>> +}
>> +
On Thu, Feb 06, 2014 at 11:24:33AM +0100, Igor Mammedov wrote:
> Windows XP shows COM2 port as non functional in
> "Device Manager" although no COM2 port backing device
> is present in QEMU.
>
> That is caused by the fact that QEMU reports to
> OSPM that device is present by setting 5th bit in
> P
On Sun, Feb 16, 2014 at 07:47:00AM -0700, Alex Williamson wrote:
> On Sun, 2014-02-16 at 13:41 +0200, Michael S. Tsirkin wrote:
> > On Fri, Feb 14, 2014 at 11:13:04PM +0100, Alexander Graf wrote:
> > >
> > > On 14.02.2014, at 23:06, Gabriel L. Somlo wrote:
> > >
> > > > On Fri, Feb 14, 2014 at 1
The Thursday 09 Jan 2014 à 09:45:14 (+0800), Stefan Hajnoczi wrote :
> On Wed, Jan 08, 2014 at 09:05:38PM +0100, Loic Dachary wrote:
> > Suppress rbd progress messages with --no-progress so they are not
> > confused with an error output when comparing test results ( progress is
> > displayed on std
Hi guys,
Starting from the patch series in 9f117d41 the below error is
observed... (reverting to the patch right before it works fine a1483f88)
Here is the error:
qemu-system-x86_64: hw/pci/pcie.c:240: pcie_cap_slot_hotplug_common:
Assertion `((pci_dev->devfn) & 0x07) == 0' failed.
Here is the c
Il 14/02/2014 17:54, Jeff Cody ha scritto:
On Tue, Feb 11, 2014 at 06:03:34PM +0100, Paolo Bonzini wrote:
Before:
$ qemu-io-old
qemu-io-old> open -r -o file.driver=nbd
qemu-io-old: can't open device (null): Could not open image: Invalid
argument
$ ./qemu-io-old
qemu-io-old>
On Fri, Feb 07, 2014 at 01:51:27PM +0100, Igor Mammedov wrote:
> Since introduction of PCIHP, it became problematic to
> punch hole in PCI0._CRS statically since PCI hotplug
> region size became runtime changeable.
What makes it runtime changeable?
> So replace static hole punching with dynamical
On Fri, Feb 07, 2014 at 01:51:35PM +0100, Igor Mammedov wrote:
> with introduction of PCIHP, MMIO range becomes changable
> at runtime so it's not possible to statically punch hole
> PCI bus _CRS.
>
> Making IO base/length available as readonly properties
> allow acpi builder to get values and res
On Fri, Feb 07, 2014 at 01:51:34PM +0100, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
> ---
> hw/i386/acpi-build.c | 10 ++
> 1 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index ce5f715..5cd0c80 100644
> --- a/h
On Fri, Feb 07, 2014 at 01:51:33PM +0100, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
> ---
> hw/i386/acpi-build.c | 62
> ++
> 1 files changed, 62 insertions(+), 0 deletions(-)
>
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.
On 16 February 2014 11:34, Michael S. Tsirkin wrote:
> Hmm no this is all wrong, from API point of view,
> devices shoud not care about value of interrupt.
> They just assert/deassert interrupts.
> It so happens that 1 means assert 0 means deassert.
Yeah, we generally model things as active-high
On Sun, 2014-02-16 at 13:41 +0200, Michael S. Tsirkin wrote:
> On Fri, Feb 14, 2014 at 11:13:04PM +0100, Alexander Graf wrote:
> >
> > On 14.02.2014, at 23:06, Gabriel L. Somlo wrote:
> >
> > > On Fri, Feb 14, 2014 at 10:21:09PM +0100, Alexander Graf wrote:
> > >>
> > >> Can't you just turn the
Il 14/02/2014 22:44, Richard Henderson ha scritto:
Ping.
On 01/31/2014 06:43 AM, Richard Henderson wrote:
There are three separate architecture extensions for logical operations,
BMI, BMI2, and TBM. The first two are supported on Intel Haswell and
AMD Excavator, while slightly earlier AMD supp
Il 31/01/2014 15:43, Richard Henderson ha scritto:
+gen_shift_maybe_vex:
+if (have_bmi2 && !const_args[2]) {
+tcg_out_vex_modrm(s, vexop + rexw, args[0], args[2], args[1]);
+break;
+}
+/* FALLTHRU */
What if args[2] happens to be ECX?
Apart f
Il 31/01/2014 15:46, Richard Henderson ha scritto:
The first 4 of these are ones that Aurelien posted some time ago,
and I reviewed, but never seemed to get committed.
The second 4 address optimization issues that I noticed with the
BMI instruction set extension, adding ANDC support to x86_64.
On Fri, Feb 07, 2014 at 01:51:32PM +0100, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
> ---
> hw/i386/acpi-build.c | 55
> ++
> 1 files changed, 55 insertions(+), 0 deletions(-)
>
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.
On Fri, Feb 07, 2014 at 01:51:31PM +0100, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
The reason I avoided doing this is that this
conflicts with qemu coding style which
only uses camel case for types.
So as a minimum this needs a comment
explaining that we are using the names from
ACPI
On Fri, Feb 14, 2014 at 11:13:04PM +0100, Alexander Graf wrote:
>
> On 14.02.2014, at 23:06, Gabriel L. Somlo wrote:
>
> > On Fri, Feb 14, 2014 at 10:21:09PM +0100, Alexander Graf wrote:
> >>
> >> Can't you just turn the polarity around in the pci host adapter?
> >
> > I tried this:
> >
> > d
On Fri, Feb 14, 2014 at 04:13:11PM -0500, Gabriel L. Somlo wrote:
> On Tue, Feb 11, 2014 at 09:54:44PM +0200, Michael S. Tsirkin wrote:
> > On Tue, Feb 11, 2014 at 01:23:31PM -0500, Gabriel L. Somlo wrote:
> > > 1. Regarding KVM and the polarity xor line in the patch above: Does
> > > anyone have e
On Fri, Feb 14, 2014 at 04:13:11PM -0500, Gabriel L. Somlo wrote:
> On Tue, Feb 11, 2014 at 09:54:44PM +0200, Michael S. Tsirkin wrote:
> > On Tue, Feb 11, 2014 at 01:23:31PM -0500, Gabriel L. Somlo wrote:
> > > 1. Regarding KVM and the polarity xor line in the patch above: Does
> > > anyone have e
On Fri, Feb 14, 2014 at 11:13:04PM +0100, Alexander Graf wrote:
>
> On 14.02.2014, at 23:06, Gabriel L. Somlo wrote:
>
> > On Fri, Feb 14, 2014 at 10:21:09PM +0100, Alexander Graf wrote:
> >>
> >> Can't you just turn the polarity around in the pci host adapter?
> >
> > I tried this:
> >
> > d
The GPTIMER uses 32-bit registers. Use a 64-bit operation to get the
ptimer count, otherwise we end up with a count of 0 for GPTIMER counter
values of 0x.
Use the GPTIMER counter value for tracing to avoid an overflow of the
32-bit value passed to trace_grlib_gptimer_enable().
Reviewed-b
On Wed, Feb 12, 2014 at 10:46:28PM +0100, Stefan Fritsch wrote:
> If VIRTIO_NET_F_CTRL_VLAN is not negotiated, do not filter out all
> VLAN-tagged packets but send them to the guest.
>
> Signed-off-by: Stefan Fritsch
Thanks for the patch.
I think there are still some issues after this
patch: we
Hi Mark,
thanks for the tip. It works fine with virtio drivers. Is there any
specific reason, why Qemu sparc64 virtualization have to use the cmd646
driver? For example mips emulator is using PIIX3/4 IDE driver.
thanks so far,
Waldemar
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