On Fri, 2021-02-12 at 10:53 -0800, Jakub Kicinski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
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> On Fri, 12 Feb 2021 15:06:41 +0100 Bjarni Jonasson wrote:
> > At Power-On Reset, transients may cause the LCPLL to lock onto a
> > clock that
On Fri, 2021-02-12 at 16:54 +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
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> On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote:
> > At Power-On Reset, transients may cause the LCPLL to lock onto a
> > clock t
On Fri, 2021-02-12 at 16:20 +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
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> On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote:
> > +static u32 vsc85xx_csr_read(struct phy_device *phydev,
> > +
Hi Bjarni,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on net/master]
url:
https://github.com/0day-ci/linux/commits/Bjarni-Jonasson/net-phy-mscc-adding-LCPLL-reset-to-VSC8514/20210212-221024
base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git
On Fri, 12 Feb 2021 15:06:41 +0100 Bjarni Jonasson wrote:
> At Power-On Reset, transients may cause the LCPLL to lock onto a
> clock that is momentarily unstable. This is normally seen in QSGMII
> setups where the higher speed 6G SerDes is being used.
> This patch adds an initial LCPLL Reset to the
At Power-On Reset, transients may cause the LCPLL to lock onto a
clock that is momentarily unstable. This is normally seen in QSGMII
setups where the higher speed 6G SerDes is being used.
This patch adds an initial LCPLL Reset to the PHY (first instance)
to avoid this issue.
Signed-off-by: Steen H
On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote:
> At Power-On Reset, transients may cause the LCPLL to lock onto a
> clock that is momentarily unstable. This is normally seen in QSGMII
> setups where the higher speed 6G SerDes is being used.
> This patch adds an initial LCPLL Reset
On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote:
> At Power-On Reset, transients may cause the LCPLL to lock onto a
> clock that is momentarily unstable. This is normally seen in QSGMII
> setups where the higher speed 6G SerDes is being used.
> This patch adds an initial LCPLL Reset
On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote:
> +static u32 vsc85xx_csr_read(struct phy_device *phydev,
> + enum csr_target target, u32 reg);
> +static int vsc85xx_csr_write(struct phy_device *phydev,
> + enum csr_target target, u3
