On Fri, Feb 12, 2021 at 03:06:41PM +0100, Bjarni Jonasson wrote:
> At Power-On Reset, transients may cause the LCPLL to lock onto a
> clock that is momentarily unstable. This is normally seen in QSGMII
> setups where the higher speed 6G SerDes is being used.
> This patch adds an initial LCPLL Reset to the PHY (first instance)
> to avoid this issue.
>
> Signed-off-by: Steen Hegelund <steen.hegel...@microchip.com>
> Signed-off-by: Bjarni Jonasson <bjarni.jonas...@microchip.com>
> Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.")
> ---
Tested-by: Vladimir Oltean <vladimir.olt...@nxp.com> # for regressions
